| Fault-tolerance techniques for SRAM-based FPGAs FL Kastensmidt, L Carro, RA da Luz Reis Springer, 2006 | 353 | 2006 |
| On the optimal design of triple modular redundancy logic for SRAM-based FPGAs FL Kastensmidt, L Sterpone, L Carro, MS Reorda Design, Automation and Test in Europe, 1290-1295, 2005 | 323 | 2005 |
| Designing fault tolerant systems into SRAM-based FPGAs F Lima, L Carro, R Reis Design Automation Conference, 2003. Proceedings, 650-655, 2003 | 204 | 2003 |
| Included in Your Digital Subscription Designing fault tolerant systems into SRAM-based FPGAs F Lima, L Carro, R Reis Design Automation Conference, 2003. Proceedings, 650-655, 2003 | 204* | 2003 |
| A fault injection analysis of Virtex FPGA TMR design methodology F Lima, C Carmichael, J Fabula, R Padovani, R Reis Radiation and Its Effects on Components and Systems, 2001. 6th European …, 2001 | 176 | 2001 |
| Designing fault-tolerant techniques for SRAM-based FPGAs FG de Lima Kastensmidt, G Neuberger, RF Hentschke, L Carro, R Reis IEEE Design & Test of Computers 21 (6), 552-562, 2004 | 174 | 2004 |
| Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy R Hentschke, F Marques, F Lima, L Carro, A Susin, R Reis Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on …, 2002 | 161 | 2002 |
| Using bulk built-in current sensors to detect soft errors EH Neto, I Ribeiro, M Vieira, G Wirth, FL Kastensmidt Ieee Micro 26 (5), 10-18, 2006 | 142 | 2006 |
| Using benchmarks for radiation testing of microprocessors and FPGAs H Quinn, WH Robinson, P Rech, M Aguirre, A Barnard, M Desogus, ... IEEE transactions on nuclear science 62 (6), 2547-2554, 2015 | 125 | 2015 |
| Single event transients in logic circuits—load and propagation induced pulse broadening G Wirth, FL Kastensmidt, I Ribeiro IEEE Transactions on Nuclear Science 55 (6), 2928-2935, 2009 | 105 | 2009 |
| A high-fault-coverage approach for the test of data, control and handshake interconnects in mesh networks-on-chip E Cota, FL Kastensmidt, M Cassel, M Hervé, P Almeida, P Meirelles, ... IEEE Transactions on Computers 57 (9), 1202-1215, 2008 | 97 | 2008 |
| Dependable network-on-chip router able to simultaneously tolerate soft errors and crosstalk AP Frantz, FL Kastensmidt, L Carro, E Cota 2006 IEEE International Test Conference, 1-9, 2006 | 87 | 2006 |
| An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories G Neuberger, FG de Lima Kastensmidt, R Reis IEEE Design & Test of Computers 22 (1), 50-58, 2005 | 74 | 2005 |
| Reconfigurable routers for low power and high performance D Matos, C Concatto, M Kreutz, F Kastensmidt, L Carro, A Susin IEEE Transactions on very large scale integration (VLSI) systems 19 (11 …, 2010 | 64 | 2010 |
| Crosstalk-and SEU-aware networks on chips AP Frantz, M Cassel, FL Kastensmidt, É Cota, L Carro IEEE Design & Test of Computers 24 (4), 340-350, 2007 | 64 | 2007 |
| FPGAs and parallel architectures for aerospace applications F Kastensmidt, P Rech Soft errors and fault-tolerant design, 2016 | 62 | 2016 |
| Designing and testing fault-tolerant techniques for sram-based fpgas FL Kastensmidt, G Neuberger, L Carro, R Reis Proceedings of the 1st conference on Computing frontiers, 419-432, 2004 | 62 | 2004 |
| An analytical model of the propagation induced pulse broadening (PIPB) effects on single event transient in flash-based FPGAs L Sterpone, N Battezzati, FL Kastensmidt, R Chipana IEEE Transactions on Nuclear science 58 (5), 2333-2340, 2011 | 60 | 2011 |
| Survey on approximate computing and its intrinsic fault tolerance G Rodrigues, F Lima Kastensmidt, A Bosio Electronics 9 (4), 557, 2020 | 59 | 2020 |
| Detecting SEEs in microprocessors through a non-intrusive hybrid technique JR Azambuja, Â Lapolli, L Rosa, FL Kastensmidt IEEE Transactions on Nuclear Science 58 (3), 993-1000, 2011 | 58 | 2011 |
Ricardo Augusto da Luz ReisUFRGS在 inf.ufrgs.br 的電子郵件地址已通過驗證
