| Bandwidth enhancement of flip-flops using feedback for high-speed integrated circuits M Sakare, SP Kumar, S Gupta IEEE Transactions on Circuits and Systems II: Express Briefs 63 (8), 768-772, 2016 | 16 | 2016 |
| Testing of high-speed DACs using PRBS generation with “Alternate-Bit-Tapping” M Singh, M Sakare, S Gupta 2011 Design, Automation & Test in Europe, 1-6, 2011 | 15 | 2011 |
| A power and area efficient architecture of a PRBS generator with multiple outputs M Sakare IEEE Transactions on Circuits and Systems II: Express Briefs 64 (8), 927-931, 2016 | 13 | 2016 |
| Full CMOS circuit for brain-inspired associative memory with on-chip trainable memristive STDP synapse SK Vohra, SA Thomas, M Sakare, DM Das IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (7), 993 …, 2023 | 12 | 2023 |
| Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons SK Vohra, SA Thomas, M Sakare, DM Das Integration 95, 102122, 2024 | 11 | 2024 |
| A high-speed PRBS generator using flip-flops employing feedback for distributed equalization M Sakare, S Gupta 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 746-749, 2014 | 11 | 2014 |
| Full CMOS implementation of bidirectional associative memory neural network with analog memristive synapse SK Vohra, S Thomas, M Sakare, DM Das 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS …, 2021 | 10 | 2021 |
| CMOS circuit implementation of spiking neural network for pattern recognition using on-chip unsupervised STDP learning SK Vohra, SA Thomas, M Sakare, DM Das arXiv preprint arXiv:2204.04430, 2022 | 8 | 2022 |
| A low power 8 × 27-1 PRBS generator using Exclusive-OR gate merged D flip-flops MK Singh, P Singh, DM Das, M Sakare 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS …, 2021 | 8 | 2021 |
| A quarter-rate 27-1 pseudo-random binary sequence generator using interleaved architecture M Sakare 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 8 | 2016 |
| A double cross-coupled delay cell for high-frequency differential ring vcos MK Singh, MK Gautam, P Singh, R Nagulapalli, DM Das, M Sakare 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 1-5, 2023 | 6 | 2023 |
| A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO MK Singh, P Singh, DM Das, M Sakare 2023 18th Conference on Ph. D Research in Microelectronics and Electronics …, 2023 | 5 | 2023 |
| A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology M Sakare, M Singh, S Gupta Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 5 | 2012 |
| A PRBS Generator using Merged XOR-D Flip-flop as Building Blocks MK Singh, P Singh, U Chichhula, H Mehra, DM Das, M Sakare Circuits, Systems, and Signal Processing 42 (11), 6813-6828, 2023 | 4 | 2023 |
| A Noise and Mismatch Improved Charge Pump for PLL in 28nm CMOS Technology H Mehra, MK Singh, ZR Sheikh, R Nagulapalli, M Sakare 2024 International Conference on Integrated Circuits, Communication, and …, 2024 | 3 | 2024 |
| Design of a PRBS generator and a serializer using active inductor employed CML latch P Singh, MK Singh, VG Hande, M Sakare 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS …, 2021 | 3 | 2021 |
| A Linearity Improved Equalizers for Short-Channel Communication Links P Singh, R Walia, R Nagulapalli, M Sakare 2024 35th Irish Signals and Systems Conference (ISSC), 1-5, 2024 | 2 | 2024 |
| Analysing mismatch effect of CMOS neurons in spiking neural network with winner-take-all mechanism SK Vohra, AP James, M Sakare, DM Das 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), 1-7, 2023 | 1 | 2023 |
| Analytical modelling of a CMOS inter spike interval decoder for resistive crossbar based brain inspired computing SK Vohra, S Thomas, M Sakare, DM Das 2021 25th International Symposium on VLSI Design and Test (VDAT), 1-4, 2021 | 1 | 2021 |
| Bandgap reference (bgr) circuit for generating bgr voltage and a method thereof M Sakare, MK Singh, R Nagulapalli US Patent App. 18/373,713, 2025 | | 2025 |
Devarshi Mrinal DasAssistant Professor, Indian Institute of Technology Ropar在 iitrpr.ac.in 的電子郵件地址已通過驗證