| Low-power multiplier design with row and column bypassing JT Yan, ZW Chen 2009 IEEE International SOC Conference (SOCC), 227-230, 2009 | 67 | 2009 |
| Construction of constrained multi-bit flip-flops for clock power reduction JT Yan, ZW Chen The 2010 International Conference on Green Circuits and Systems, 675-678, 2010 | 58 | 2010 |
| Low-cost low-power bypassing-based multiplier design JT Yan, ZW Chen Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 36 | 2010 |
| Routability-driven flip-flop merging process for clock power reduction ZW Chen, JT Yan 2010 IEEE International Conference on Computer Design, 203-208, 2010 | 33 | 2010 |
| An improved optimal algorithm for bubble-sorting-based non-Manhattan channel routing JT Yan IEEE transactions on computer-aided design of integrated circuits and …, 1999 | 30 | 1999 |
| Obstacle-aware length-matching bus routing JT Yan, ZW Chen Proceedings of the 2011 international symposium on Physical design, 61-68, 2011 | 28 | 2011 |
| Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction JT Yan ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (2 …, 2008 | 28 | 2008 |
| Timing-constrained congestion-driven global routing JT Yan, SH Lin ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004 | 25 | 2004 |
| A Fuzzy clustering-algorithm for graph bisection JT Yan, PY Hsiao Information Processing Letters 52 (5), 259-263, 1994 | 25 | 1994 |
| Routability-constrained multi-bit flip-flop construction for clock power reduction ZW Chen, JT Yan Integration 46 (3), 290-300, 2013 | 24 | 2013 |
| Electromigration-aware rectilinear steiner tree construction for analog circuits JT Yan, ZW Chen APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 1692-1695, 2008 | 18 | 2008 |
| IO connection assignment and RDL routing for flip-chip designs JTYZW Chen Asia and South Pacific Design Automation Conference, 588-593, 2009 | 17* | 2009 |
| Yield-driven redundant via insertion based on probabilistic via-connection analysis JT Yan, BY Chiang, ZW Chen 2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006 | 17 | 2006 |
| Single-layer GNR routing for minimization of bending delay JT Yan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 15 | 2019 |
| Printed circuit board routing and package layout codesign SS Chen, WD Tseng, JT Yan, SJ Chen Asia-Pacific Conference on Circuits and Systems 1, 155-158, 2002 | 14 | 2002 |
| Ordered escape routing via routability-driven pin assignment JT Yan, CW Ke, ZW Chen Proceedings of the 20th symposium on Great lakes symposium on VLSI, 417-422, 2010 | 13 | 2010 |
| Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance JT Yan, ZW Chen 2011 Design, Automation & Test in Europe, 1-6, 2011 | 12 | 2011 |
| Thermal via planning for temperature reduction in 3D ICs JT Yan, YC Chang, ZW Chen 23rd IEEE International SOC Conference, 392-395, 2010 | 12 | 2010 |
| Single-layer delay-driven GNR nontree routing under resource constraint for yield improvement JT Yan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (3), 736-749, 2020 | 11 | 2020 |
| Construction of delay-driven GNR routing tree JT Yan, CH Yen 2019 17th IEEE International new circuits and systems conference (NEWCAS), 1-4, 2019 | 11 | 2019 |
Chia-Heng YenNational Taiwan Ocean University在 ntou.edu.tw 的電子郵件地址已通過驗證