| Gate-length biasing for runtime-leakage control P Gupta, AB Kahng, P Sharma, D Sylvester IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 133 | 2006 |
| Selective gate-length biasing for cost-effective runtime leakage control P Gupta, AB Kahng, P Sharma, D Sylvester Proceedings of the 41st annual Design Automation Conference, 327-330, 2004 | 116 | 2004 |
| Exploiting STI stress for performance AB Kahng, P Sharma, RO Topaloglu 2007 IEEE/ACM International Conference on Computer-Aided Design, 83-90, 2007 | 95 | 2007 |
| Study of floating fill impact on interconnect capacitance AB Kahng, K Samadi, P Sharma 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-696, 2006 | 47 | 2006 |
| Chip optimization through STI-stress-aware placement perturbations and fill insertion AB Kahng, P Sharma, RO Topaloglu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 43 | 2008 |
| Lithography simulation-based full-chip design analyses P Gupta, AB Kahng, S Nakagawa, S Shah, P Sharma Design and Process Integration for Microelectronic Manufacturing IV 6156 …, 2006 | 36 | 2006 |
| Defocus-aware leakage estimation and control AB Kahng, S Muddu, P Sharma Proceedings of the 2005 international symposium on Low power electronics and …, 2005 | 33 | 2005 |
| Interconnect modeling for improved system-level design optimization L Carloni, AB Kahng, S Muddu, A Pinto, K Samadi, P Sharma 2008 Asia and South Pacific Design Automation Conference, 258-264, 2008 | 32 | 2008 |
| Layout-aware scan chain synthesis for improved path delay fault coverage P Gupta, AB Kahng, II Mandoiu, P Sharma IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 26 | 2005 |
| A practical transistor-level dual threshold voltage assignment methodology P Gupta, AB Kahng, P Sharma Sixth international symposium on quality electronic design (isqed'05), 421-426, 2005 | 24 | 2005 |
| Eyecharts: Constructive benchmarking of gate sizing heuristics P Gupta, AB Kahng, A Kasibhatla, P Sharma Proceedings of the 47th Design Automation Conference, 597-602, 2010 | 23 | 2010 |
| Integrated circuit with degradation monitoring MS Abadir, P Sharma US Patent 9,329,229, 2016 | 22 | 2016 |
| Fill for shallow trench isolation CMP AB Kahng, P Sharma, A Zelikovsky Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 21 | 2006 |
| Accurate predictive interconnect modeling for system-level design LP Carloni, AB Kahng, SV Muddu, A Pinto, K Samadi, P Sharma IEEE transactions on very large scale integration (VLSI) systems 18 (4), 679-684, 2009 | 17 | 2009 |
| Method and system for wafer topography-aware integrated circuit design analysis and optimization P Gupta, A Kahng, P Sharma, S Muddu US Patent 8,024,675, 2011 | 16 | 2011 |
| Lens aberration aware timing-driven placement AB Kahng, CH Park, P Sharma, Q Wang Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 16 | 2006 |
| Impact of gate-length biasing on threshold-voltage selection AB Kahng, S Muddu, P Sharma 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-754, 2006 | 14 | 2006 |
| Joining the design and mask flows for better and cheaper masks P Gupta, AB Kahng, CH Park, P Sharma, DMC Sylvester, J Yang 24th Annual BACUS Symposium on Photomask Technology 5567, 318-329, 2004 | 13 | 2004 |
| Integrated circuit device with reduced leakage and method therefor P Sharma, MS Abadir, SP Warrick US Patent 8,898,614, 2014 | 12 | 2014 |
| Integrated circuit with degradation monitoring P Sharma, MA Thompson, WE Conley US Patent 9,229,051, 2016 | 11 | 2016 |
PUNEET GUPTAUCLA Electrical and Computer Engineering在 g.ucla.edu 的电子邮件经过验证
