| Adaptive performance compensation with in-situ timing error predictive sensors for subthreshold circuits H Fuketa, M Hashimoto, Y Mitsuyama, T Onoye IEEE Transactions on very large scale integration (VLSI) systems 20 (2), 333-343, 2011 | 78 | 2011 |
| Neutron induced single event multiple transients with voltage scaling and body biasing R Harada, Y Mitsuyama, M Hashimoto, T Onoye 2011 International Reliability Physics Symposium, 3C. 4.1-3C. 4.5, 2011 | 77 | 2011 |
| When single event upset meets deep neural networks: Observations, explorations, and remedies Z Yan, Y Shi, W Liao, M Hashimoto, X Zhou, C Zhuo 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 163-168, 2020 | 66 | 2020 |
| Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies Z Huang, A Kurokawa, M Hashimoto, T Sato, M Jiang, Y Inoue IEEE transactions on computer-aided design of integrated circuits and …, 2010 | 64 | 2010 |
| On-chip thermal gradient analysis and temperature flattening for SoC design T Sato, J Ichimiya, N Ono, K Hachiya, M Hashimoto Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 63 | 2005 |
| A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process T Miyazaki, M Hashimoto, H Onodera ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004 | 59 | 2004 |
| A performance optimization method by gate sizing using statistical static timing analysis M Hashimoto, H Onodera Proceedings of the 2000 international symposium on Physical design, 111-116, 2000 | 52 | 2000 |
| Statistical analysis of clock skew variation in H-tree structure M Hashimoto, T Yamamoto, H Onodera Sixth international symposium on quality electronic design (isqed'05), 402-407, 2005 | 51 | 2005 |
| All-digital ring-oscillator-based macro for sensing dynamic supply noise waveform Y Ogasahara, M Hashimoto, T Onoye IEEE journal of solid-state circuits 44 (6), 1745-1755, 2009 | 50 | 2009 |
| Coarse-grained dynamically reconfigurable architecture with flexible reliability D Alnajiar, Y Ko, T Imagawa, H Konoura, M Hiromoto, Y Mitsuyama, ... 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 49 | 2009 |
| Increase in delay uncertainty by performance optimization M Hashimoto, H Onodeva ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001 | 45 | 2001 |
| Equivalent waveform propagation for static timing analysis M Hashimoto, Y Yamada, H Onodera IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 44 | 2004 |
| Post-layout transistor sizing for power reduction in cell-based design M Hashimoto, H Onodera Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001 | 44 | 2001 |
| A power optimization method considering glitch reduction by gate sizing M Hashimoto, H Onodera, K Tamaru Proceedings of the 1998 international symposium on Low power electronics and …, 1998 | 43 | 1998 |
| Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement Y Ogasahara, T Enami, M Hashimoto, T Sato, T Onoye IEEE Transactions on Circuits and Systems II: Express Briefs 54 (10), 868-872, 2007 | 42 | 2007 |
| Effects of on-chip inductance on power distribution grid A Muramatsu, M Hashimoto, H Onodera Proceedings of the 2005 international symposium on Physical design, 63-69, 2005 | 42 | 2005 |
| Implementing flexible reliability in a coarse-grained reconfigurable architecture D Alnajjar, H Konoura, Y Ko, Y Mitsuyama, M Hashimoto, T Onoye IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (12 …, 2012 | 40 | 2012 |
| Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise T Enami, S Ninomiya, M Hashimoto Proceedings of the 2008 international symposium on Physical design, 160-167, 2008 | 40 | 2008 |
| Timing analysis considering temporal supply voltage fluctuation M Hashimoto, J Yamaguchi, T Sato, H Onodera Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 40 | 2005 |
| Measurement circuits for acquiring SET pulse width distribution with sub-FO1-inverter-delay resolution R Harada, Y Mitsuyama, M Hashimoto, T Onoye IEICE Transactions on Fundamentals of Electronics, Communications and …, 2010 | 38 | 2010 |
Takao OnoyeOsaka University在 ist.osaka-u.ac.jp 的电子邮件经过验证