| An injectable 64 nW ECG mixed-signal SoC in 65 nm for arrhythmia monitoring YP Chen, D Jeon, Y Lee, Y Kim, Z Foo, I Lee, NB Langhals, G Kruger, ... IEEE Journal of Solid-State Circuits 50 (1), 375-390, 2014 | 207 | 2014 |
| A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS D Jeon, M Seok, C Chakrabarti, D Blaauw, D Sylvester IEEE Journal of Solid-State Circuits 47 (1), 23-34, 2011 | 113 | 2011 |
| 24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis D Jeon, YP Chen, Y Lee, Y Kim, Z Foo, G Kruger, H Oral, O Berenfeld, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 97 | 2014 |
| A 0.27 V 30MHz 17.7 nJ/transform 1024-pt complex FFT core with super-pipelining M Seok, D Jeon, C Chakrabarti, D Blaauw, D Sylvester 2011 IEEE International Solid-State Circuits Conference, 342-344, 2011 | 86 | 2011 |
| 7.6 A 65nm 236.5 nJ/classification neuromorphic processor with 7.5% energy overhead on-chip learning using direct spike-only feedback J Park, J Lee, D Jeon 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 140-142, 2019 | 83 | 2019 |
| A 23-mW face recognition processor with mostly-read 5T memory in 40-nm CMOS D Jeon, Q Dong, Y Kim, X Wang, S Chen, H Yu, D Blaauw, D Sylvester IEEE Journal of Solid-State Circuits 52 (6), 1628-1642, 2017 | 72 | 2017 |
| Real-time denoising and dereverberation wtih tiny recurrent u-net HS Choi, S Park, JH Lee, H Heo, D Jeon, K Lee ICASSP 2021-2021 IEEE International Conference on Acoustics, Speech and …, 2021 | 64 | 2021 |
| A 65-nm neuromorphic image classification processor with energy-efficient training through direct spike-only feedback J Park, J Lee, D Jeon IEEE Journal of Solid-State Circuits 55 (1), 108-119, 2019 | 51 | 2019 |
| Enhancing reliability of analog neural network processors S Moon, K Shin, D Jeon IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (6 …, 2019 | 48 | 2019 |
| Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design M Seok, D Jeon, C Chakrabarti, D Blaauw, D Sylvester Proceedings of the 48th Design Automation Conference, 990-995, 2011 | 43 | 2011 |
| 9.3 a 40nm 4.81 TFLOPS/W 8b floating-point training processor for non-sparse neural networks using shared exponent bias and 24-way fused multiply-add tree J Park, S Lee, D Jeon 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 1-3, 2021 | 41 | 2021 |
| An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With W/Channel in 65-nm CMOS AT Do, SMA Zeinolabedin, D Jeon, D Sylvester, TTH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 126-137, 2018 | 40 | 2018 |
| Memory with segmented error correction codes M Goel, D Jeon US Patent 8,745,472, 2014 | 40 | 2014 |
| An energy efficient full-frame feature extraction accelerator with shift-latch FIFO in 28 nm CMOS D Jeon, MB Henry, Y Kim, I Lee, Z Zhang, D Blaauw, D Sylvester IEEE Journal of Solid-State Circuits 49 (5), 1271-1284, 2014 | 38 | 2014 |
| Design methodology for voltage-overscaled ultra-low-power systems D Jeon, M Seok, Z Zhang, D Blaauw, D Sylvester IEEE Transactions on Circuits and Systems II: Express Briefs 59 (12), 952-956, 2012 | 38 | 2012 |
| A noise reconfigurable all-digital phase-locked loop using a switched capacitor-based frequency-locked loop and a noise detector T Jang, S Jeong, D Jeon, KD Choo, D Sylvester, D Blaauw IEEE Journal of Solid-State Circuits 53 (1), 50-65, 2017 | 28 | 2017 |
| A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2per channel in 65-nm CMOS SMA Zeinolabedin, AT Do, D Jeon, D Sylvester, TTH Kim 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 28 | 2016 |
| A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory D Jeon, Q Dong, Y Kim, X Wang, S Chen, H Yu, D Blaauw, D Sylvester 2015 Symposium on VLSI Circuits (VLSI Circuits), C48-C49, 2015 | 27 | 2015 |
| A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications S Jeong, W Jung, D Jeon, O Berenfeld, H Oral, G Kruger, D Blaauw, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C60-C61, 2015 | 25 | 2015 |
| A neural network training processor with 8-bit shared exponent bias floating point and multiple-way fused multiply-add trees J Park, S Lee, D Jeon IEEE Journal of Solid-State Circuits 57 (3), 965-977, 2021 | 24 | 2021 |
