| Semiconductor device for testing large number of devices and composing method and test method thereof WON Hyosig, H DaiJoon, K Jeong US Patent 10,026,661, 2018 | 92 | 2018 |
| 32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography RT Greenway, K Jeong, AB Kahng, CH Park, JS Petersen Photomask Technology 2008 7122, 528-539, 2008 | 86 | 2008 |
| An MTCMOS design methodology and its application to mobile computing HS Won, KS Kim, KO Jeong, KT Park, KM Choi, JT Kong Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 81 | 2003 |
| Impact of guardband reduction on design outcomes: A quantitative approach K Jeong, AB Kahng, K Samadi IEEE Transactions on Semiconductor Manufacturing 22 (4), 552-565, 2009 | 55 | 2009 |
| Accurate machine-learning-based on-chip router modeling K Jeong, AB Kahng, B Lin, K Samadi IEEE Embedded Systems Letters 2 (3), 62-66, 2010 | 52 | 2010 |
| Interference assisted lithography for patterning of 1D gridded design RT Greenway, R Hendel, K Jeong, AB Kahng, JS Petersen, Z Rao, ... Alternative Lithographic Technologies 7271, 741-751, 2009 | 44 | 2009 |
| MAPG: Memory access power gating K Jeong, AB Kahng, S Kang, TS Rosing, R Strong 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 36 | 2012 |
| Methodology from chaos in IC implementation K Jeong, AB Kahng 2010 11th International Symposium on Quality Electronic Design (ISQED), 885-892, 2010 | 31 | 2010 |
| Timing yield-aware color reassignment and detailed placement perturbation for bimodal CD distribution in double patterning lithography M Gupta, K Jeong, AB Kahng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 30 | 2010 |
| A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS) K Jeong, AB Kahng 2009 International SoC Design Conference (ISOCC), 49-52, 2009 | 30 | 2009 |
| Revisiting the linear programming framework for leakage power vs. performance optimization K Jeong, AB Kahng, H Yao 2009 10th International Symposium on Quality Electronic Design, 127-134, 2009 | 30 | 2009 |
| Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography K Jeong, AB Kahng 2009 Asia and South Pacific Design Automation Conference, 486-491, 2009 | 30 | 2009 |
| Is overlay error more important than interconnect variations in double patterning? K Jeong, AB Kahng, RO Topaloglu Proceedings of the 11th international workshop on System level interconnect …, 2009 | 28 | 2009 |
| Assessing chip-level impact of double patterning lithography K Jeong, AB Kahng, RO Topaloglu 2010 11th International Symposium on Quality Electronic Design (ISQED), 122-130, 2010 | 27 | 2010 |
| Quantified impacts of guardband reduction on design process outcomes K Jeong, AB Kahng, K Samadi 9th International Symposium on Quality Electronic Design (isqed 2008), 790-797, 2008 | 21 | 2008 |
| Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography M Gupta, K Jeong, AB Kahng Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 19 | 2009 |
| Electrical metrics for lithographic line-end tapering P Gupta, K Jeong, AB Kahng, CH Park Photomask and Next-Generation Lithography Mask Technology XV 7028, 977-988, 2008 | 19 | 2008 |
| MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop H Won, K Jeong, YH Kim, BH Lee US Patent 7,453,300, 2008 | 16 | 2008 |
| Double patterning layout design method TJ Song, JH Park, K Jeong US Patent 9,098,670, 2015 | 15 | 2015 |
| Method of designing layout of semiconductor device K Jeong US Patent 9,811,626, 2017 | 11 | 2017 |
Kambiz SamadiQualcomm Research在 qti.qualcomm.com 的电子邮件经过验证