| A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path Y Hu, T Siriburanon, RB Staszewski IEEE Journal of Solid-State Circuits 53 (7), 1977-1987, 2018 | 154 | 2018 |
| Oscillator flicker phase noise: A tutorial Y Hu, T Siriburanon, RB Staszewski IEEE Transactions on Circuits and Systems II: Express Briefs 68 (2), 538-544, 2020 | 58 | 2020 |
| 17.6 A 21.7-to-26.5 GHz charge-sharing locking quadrature PLL with implicit digital frequency-tracking loop achieving 75fs jitter and− 250dB FoM Y Hu, X Chen, T Siriburanon, J Du, Z Gao, V Govindaraj, A Zhu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 276-278, 2020 | 51 | 2020 |
| Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillators Y Hu, T Siriburanon, RB Staszewski IEEE Transactions on Circuits and Systems II: Express Briefs 66 (12), 1962-1966, 2019 | 38 | 2019 |
| A charge-sharing locking technique with a general phase noise theory of injection locking Y Hu, X Chen, T Siriburanon, J Du, V Govindaraj, A Zhu, RB Staszewski IEEE Journal of Solid-State Circuits 57 (2), 518-534, 2021 | 29 | 2021 |
| A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner Y Hu, T Siriburanon, RB Staszewski ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 87-90, 2017 | 24 | 2017 |
| A 2.02–2.87-GHz− 249-dB FoM 1.1-mW digital PLL exploiting reference-sampling phase detector J Du, T Siriburanon, Y Hu, V Govindaraj, RB Staszewski IEEE Solid-State Circuits Letters 3, 158-161, 2020 | 21 | 2020 |
| A reference-waveform oversampling technique in a fractional-N ADPLL J Du, T Siriburanon, Y Hu, V Govindaraj, RB Staszewski IEEE Journal of Solid-State Circuits 56 (11), 3445-3457, 2021 | 20 | 2021 |
| A Tiny Complementary Oscillator With 1/f3 Noise Reduction Using a Triple-8-Shaped Transformer X Chen, Y Hu, T Siriburanon, J Du, RB Staszewski, A Zhu IEEE Solid-State Circuits Letters 3, 162-165, 2020 | 19 | 2020 |
| A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range J Du, Y Hu, T Siriburanon, E Kobal, P Quinlan, A Zhu, RB Staszewski IEEE Journal of Solid-State Circuits 57 (2), 452-464, 2021 | 18 | 2021 |
| A Millimeter-Wave ADPLL With Reference Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N J Du, T Siriburanon, X Chen, Y Hu, V Govindaraj, A Zhu, RB Staszewski IEEE Solid-State Circuits Letters 4, 214-217, 2021 | 16 | 2021 |
| A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28 … J Du, Y Hu, T Siriburanon, RB Staszewski 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 15 | 2019 |
| A 24–31 GHz Reference Oversampling ADPLL Achieving FoMjitter−N of -269.3 dB J Du, T Siriburanon, X Chen, Y Hu, V Govindaraj, A Zhu, RB Staszewski 2021 Symposium on VLSI Circuits, 1-2, 2021 | 14 | 2021 |
| Flicker noise upconversion and reduction mechanisms in RF/millimeter-wave oscillators for 5G communications Y Hu | 13 | 2019 |
| An 18.8-to-23.3 GHz ADPLL based on charge-steering-sampling technique achieving 75.9 fs RMS jitter and–252 dB FoM W Tao, W Zhao, RB Staszewski, F Lin, Y Hu 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 11 | 2023 |
| A 30-GHz class-F quadrature DCO using phase shifts between drain–gate–source for low flicker phase noise and I/Q exactness X Chen, Y Hu, T Siriburanon, J Du, RB Staszewski, A Zhu IEEE Journal of Solid-State Circuits 58 (7), 1945-1958, 2023 | 11 | 2023 |
| Multirate timestamp modeling for ultralow-jitter frequency synthesis: A tutorial Y Hu, T Siriburanon, RB Staszewski IEEE Transactions on Circuits and Systems II: Express Briefs 69 (7), 3030-3036, 2022 | 10 | 2022 |
| Flicker phase-noise reduction using gate–drain phase shift in transformer-based oscillators X Chen, Y Hu, T Siriburanon, J Du, RB Staszewski, A Zhu IEEE Transactions on Circuits and Systems I: Regular Papers 69 (3), 973-984, 2021 | 10 | 2021 |
| A digital-to-time converter based on crystal oscillator waveform achieving 86-fs jitter in 22-nm FD-SOI CMOS X Chen, T Siriburanon, Z Wang, J Du, Y Hu, A Zhu, RB Staszewski 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 319-322, 2022 | 5 | 2022 |
| Dtc-assisted all-digital phase-locked loop exploiting hybrid time/voltage phase digitization V Govindaraj, J Du, Y Hu, T Siriburanon, RB Staszewski 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 81-84, 2019 | 5 | 2019 |
Robert Bogdan StaszewskiUniversity College Dublin (UCD)Email được xác minh tại ucd.ie