Theo dõi
David A. Wood
David A. Wood
University of Wisconsin, Madison
Email được xác minh tại cs.wisc.edu - Trang chủ
Tiêu đề
Trích dẫn bởi
Trích dẫn bởi
Năm
The gem5 simulator
N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ...
ACM SIGARCH computer architecture news 39 (2), 1-7, 2011
63172011
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
MMK Martin, DJ Sorin, BM Beckmann, MR Marty, M Xu, AR Alameldeen, ...
ACM SIGARCH Computer Architecture News 33 (4), 92-99, 2005
21242005
Implementation techniques for main memory database systems
DJ DeWitt, RH Katz, F Olken, LD Shapiro, MR Stonebraker, DA Wood
ACM SIGMOD Record 14 (2), 1-8, 1984
13531984
LogTM: Log-based transactional memory
KE Moore, J Bobba, MJ Moravan, MD Hill, DA Wood
Proceedings of the 12th International Symposium on High-Performance Computer …, 2006
9752006
DBMSs on a modern processor: Where does time go?
A Ailamaki, DJ DeWitt, MD Hill, DA Wood
Proceedings of the International Conference on Very Large Data Bases, 266-277, 1999
7611999
Tempest and Typhoon: User-level shared memory
SK Reinhardt, JR Larus, DA Wood
Proceedings of the 21st annual international symposium on Computer …, 1994
5531994
A primer on memory consistency and cache coherence
D Sorin, M Hill, D Wood
Morgan & Claypool Publishers, 2011
5292011
The wisconsin wind tunnel: Virtual prototyping of parallel computers
SK Reinhardt, MD Hill, JR Larus, AR Lebeck, JC Lewis, DA Wood
Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and …, 1993
5271993
Managing wire delay in large chip-multiprocessor caches
BM Beckmann, DA Wood
37th International Symposium on Microarchitecture (MICRO-37'04), 319-330, 2004
5012004
LogTM-SE: Decoupling hardware transactional memory from caches
L Yen, J Bobba, MR Marty, KE Moore, H Volos, MD Hill, MM Swift, ...
2007 IEEE 13th International Symposium on High Performance Computer …, 2007
4772007
Adaptive cache compression for high-performance processors
AR Alameldeen, DA Wood
ACM SIGARCH Computer Architecture News 32 (2), 212, 2004
4492004
SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery
DJ Sorin, MMK Martin, MD Hill, DA Wood
ACM SIGARCH Computer Architecture News 30 (2), 123-134, 2002
4282002
Token coherence: Decoupling performance and correctness
MMK Martin, MD Hill, DA Wood
ACM SIGARCH Computer Architecture News 31 (2), 182-193, 2003
4272003
Implementing a cache consistency protocol
RH Katz, SJ Eggers, DA Wood, CL Perkins, RG Sheldon
ACM SIGARCH Computer Architecture News 13 (3), 276-283, 1985
4261985
Fine-grain access control for distributed shared memory
I Schoinas, B Falsafi, AR Lebeck, SK Reinhardt, JR Larus, DA Wood
Proceedings of the sixth international conference on Architectural support …, 1994
3961994
Frequent pattern compression: A significance-based compression scheme for L2 caches
AR Alameldeen, DA Wood
Dept. of Computer Sciences, University of Wisconsin-Madison, Tech. Rep, 2004
3752004
Variability in architectural simulations of multi-threaded workloads
AR Alameldeen, DA Wood
The Ninth International Symposium on High-Performance Computer Architecture …, 2003
3642003
The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
3482020
Cache profiling and the SPEC benchmarks: A case study
AR Lebeck, DA Wood
Computer 27 (10), 15-26, 1994
3441994
gem5-gpu: A heterogeneous cpu-gpu simulator
J Power, J Hestness, MS Orr, MD Hill, DA Wood
IEEE Computer Architecture Letters 14 (1), 34-36, 2014
3392014
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