Các bài viết có thể truy cập công khai - Sachin SapatnekarTìm hiểu thêm
Không có ở bất kỳ nơi nào: 5
An Ising solver chip based on coupled ring oscillators with a 48-node all-to-all connected array architecture
H Lo, W Moy, H Yu, S Sapatnekar, CH Kim
Nature Electronics 6 (10), 771-778, 2023
Các cơ quan ủy nhiệm: US Department of Defense
Machine Learning for Analog Layout
SM Burns, H Chen, T Dhar, R Harjani, J Hu, N Karmokar, K Kunal, Y Li, ...
Machine Learning Applications in Electronic Design Automation, 505-544, 2022
Các cơ quan ủy nhiệm: US National Science Foundation, US Department of Defense
A generalized methodology for well island generation and well-tap insertion in analog/mixed-signal layouts
RS Gopalakrishnan, M Madhusudan, AK Sharma, J Poojary, S Yaldiz, ...
ACM Transactions on Design Automation of Electronic Systems 28 (5), 1-25, 2023
Các cơ quan ủy nhiệm: US Department of Defense
Control synthesis and delay sensor deployment for efficient ASV designs
C Li, SS Sapatnekar, J Hu
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2016
Các cơ quan ủy nhiệm: US National Science Foundation
Reinforcing the Connection between Analog Design and EDA
K Kunal, M Madhusudan, J Poojary, S Ramprasath, AK Sharma, ...
2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 665-670, 2024
Các cơ quan ủy nhiệm: US National Science Foundation, US Department of Defense
Có tại một số nơi: 110
Toward an open-source digital flow: First learnings from the openroad project
T Ajayi, VA Chhabria, M Fogaça, S Hashemi, A Hosny, AB Kahng, M Kim, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019
Các cơ quan ủy nhiệm: US Department of Defense
OpenROAD: Toward a self-driving, open-source digital layout implementation tool chain
T Ajayi, D Blaauw
Proceedings of Government Microcircuit Applications and Critical Technology …, 2019
Các cơ quan ủy nhiệm: US National Science Foundation, US Department of Defense
In-memory processing on the spintronic CRAM: From hardware design to application mapping
M Zabihi, ZI Chowdhury, Z Zhao, UR Karpuzcu, JP Wang, SS Sapatnekar
IEEE Transactions on Computers 68 (8), 1159-1173, 2018
Các cơ quan ủy nhiệm: US National Science Foundation, US Department of Defense
ALIGN: Open-source analog layout automation from the ground up
K Kunal, M Madhusudan, AK Sharma, W Xu, SM Burns, R Harjani, J Hu, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019
Các cơ quan ủy nhiệm: US Department of Defense
A 1,968-node coupled ring oscillator circuit for combinatorial optimization problem solving
W Moy, I Ahmed, P Chiu, J Moy, SS Sapatnekar, CH Kim
Nature Electronics 5 (5), 310-317, 2022
Các cơ quan ủy nhiệm: US National Science Foundation
A customized graph neural network model for guiding analog IC placement
Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, SS Sapatnekar, R Harjani, ...
Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020
Các cơ quan ủy nhiệm: US Department of Defense
GANA: Graph convolutional network based automated netlist annotation for analog circuits
K Kunal, T Dhar, M Madhusudan, J Poojary, A Sharma, W Xu, SM Burns, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2020
Các cơ quan ủy nhiệm: US Department of Defense
A simple yet efficient accuracy-configurable adder design
W Xu, SS Sapatnekar, J Hu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (6 …, 2018
Các cơ quan ủy nhiệm: US National Science Foundation
Efficient in-memory processing using spintronics
Z Chowdhury, JD Harms, SK Khatamifard, M Zabihi, Y Lv, AP Lyle, ...
IEEE Computer Architecture Letters 17 (1), 42-46, 2017
Các cơ quan ủy nhiệm: US National Science Foundation, US Department of Defense
Thermal and IR drop analysis using convolutional encoder-decoder networks
VA Chhabria, V Ahuja, A Prabhu, N Patil, P Jain, SS Sapatnekar
Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021
Các cơ quan ủy nhiệm: US Department of Defense
ALIGN: A system for automating analog layout
T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ...
IEEE Design & Test 38 (2), 8-18, 2020
Các cơ quan ủy nhiệm: US Department of Defense
A comparative study between spin-transfer-torque and spin-Hall-effect switching mechanisms in PMTJ using SPICE
I Ahmed, Z Zhao, MG Mankalale, SS Sapatnekar, JP Wang, CH Kim
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3 …, 2017
Các cơ quan ủy nhiệm: US National Science Foundation, US Department of Defense
Estimating circuit aging due to BTI and HCI using ring-oscillator-based sensors
D Sengupta, SS Sapatnekar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
Các cơ quan ủy nhiệm: US National Science Foundation
A general approach for identifying hierarchical symmetry constraints for analog circuit layout
K Kunal, J Poojary, T Dhar, M Madhusudan, R Harjani, SS Sapatnekar
Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020
Các cơ quan ủy nhiệm: US Department of Defense
Optimal design of JPEG hardware under the approximate computing paradigm
FS Snigdha, D Sengupta, J Hu, SS Sapatnekar
Proceedings of the 53rd annual design automation conference, 1-6, 2016
Các cơ quan ủy nhiệm: US National Science Foundation
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