| VIS: A system for verification and synthesis RK Brayton, GD Hachtel, A Sangiovanni-Vincentelli, F Somenzi, A Aziz, ... Computer Aided Verification: 8th International Conference, CAV'96 New …, 1996 | 980 | 1996 |
| Delay-optimal technology mapping by DAG covering Y Kukimoto, RK Brayton, P Sawkar Proceedings Of The 35th Annual Design Automation Conference, 348-351, 1998 | 135 | 1998 |
| Application of Boolean unification to combinational logic synthesis M Fujita, Y Tamiya, Y Kukimoto, KC Chen 1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991 | 65 | 1991 |
| Vis RK Brayton, GD Hachtel, A Sangiovanni-Vincentelli, F Somenzi, A Aziz, ... Formal Methods in Computer-Aided Design: First International Conference …, 1996 | 48 | 1996 |
| Rectification method for lookup-table type FPGA's Kukimoto, Fujita 1992 IEEE/ACM International Conference on Computer-Aided Design, 54-61, 1992 | 48 | 1992 |
| Hierarchical functional timing analysis Y Kukimoto, RK Brayton Proceedings of the 35th annual Design Automation Conference, 580-585, 1998 | 32 | 1998 |
| Refining switching window by time slots for crosstalk noise calculation P Chen, Y Kukimoto, K Keutzer Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 31 | 2002 |
| Exact required time analysis via false path detection Y Kukimoto, RK Brayton Proceedings of the 34th annual Design Automation Conference, 220-225, 1997 | 27 | 1997 |
| BDD minimization by truth table permutations M Fujita, Y Kukimoto, RK Brayton 1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996 | 26 | 1996 |
| On convergence of switching windows computation in presence of crosstalk noise P Chen, Y Kukimoto, CC Teng, K Keutzer Proceedings of the 2002 international symposium on Physical design, 84-89, 2002 | 25 | 2002 |
| Approximate timing analysis of combinational circuits under the XBDO model Kukimoto, Gosti, Saldanha, Brayton 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997 | 24 | 1997 |
| VIS user's manual T Villa, G Swamy, T Shiple University of California, Berkeley, Tech. Rep. UCB/ERL M95/104, December 20 …, 1995 | 24 | 1995 |
| Blif-mv Y Kukimoto The VIS Group, University California, Berkely, 1996 | 18 | 1996 |
| Static timing analysis Y Kukimoto, M Berkelaar, K Sakallah Logic Synthesis and Verification, 373-401, 2002 | 14 | 2002 |
| Timing-safe false path removal for combinational modules Y Kukimoto, RK Brayton 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999 | 14 | 1999 |
| A redesign technique for combinational circuits based on gate reconnections Y Kukimoto, M Fujita, RK Brayton Proceedings of the 1994 IEEE/ACM international conference on Computer-aided …, 1994 | 14 | 1994 |
| Delay-Optimal Technology Mapping by DAG Covering, Dept. of Electrical Engineering and Computer Science Y Kukimoto, RK Brayton, P Sawkar University of California, Berkeley, Strategic CAD Laboratories, Intel Corp, 1997 | 13 | 1997 |
| Canonical TBDD’s and their application to combinational verification EI Goldberg, Y Kukimoto, RK Brayton Proc. IWLS, 1997 | 10 | 1997 |
| Computing Delay with Coupling using Timed Automata S Tasıran, Y Kukimoto, RK Brayton Proceedings of the 1997 ACM/IEEE International Workshop on Timing Issues in …, 1997 | 9 | 1997 |
| Patching method for lookup-table type FPGA's M Fujita, Y Kukimoto International Workshop on Field Programmable Logic and Applications, 61-70, 1992 | 8 | 1992 |
