Theo dõi
Min-Jae Seo
Min-Jae Seo
서울시립대학교
Email được xác minh tại uos.ac.kr - Trang chủ
Tiêu đề
Trích dẫn bởi
Trích dẫn bởi
Năm
A 0.6 V 12 b 10 MS/s low-noise asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC
W Kim, HK Hong, YJ Roh, HW Kang, SI Hwang, DS Jo, DJ Chang, ...
IEEE journal of solid-state circuits 51 (8), 1826-1839, 2016
982016
A reusable code-based SAR ADC design with CDAC compiler and synthesizable analog building blocks
MJ Seo, YJ Roh, DJ Chang, W Kim, YD Kim, ST Ryu
IEEE Transactions on circuits and systems II: Express Briefs 65 (12), 1904-1908, 2018
492018
A 4.2-mW 10-MHz BW 74.4-dB SNDR continuous-time delta-sigma modulator with SAR-assisted digital-domain noise coupling
IH Jang, MJ Seo, SH Cho, JK Lee, SY Baek, S Kwon, M Choi, HJ Ko, ...
IEEE Journal of Solid-State Circuits 53 (4), 1139-1148, 2017
332017
A 2.7-M pixels 64-mW CMOS image sensor with multicolumn-parallel noise-shaping SAR ADCs
SI Hwang, JH Chung, HJ Kim, IH Jang, MJ Seo, SH Cho, H Kang, M Kwon, ...
IEEE Transactions on Electron Devices 65 (3), 1119-1126, 2018
282018
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS
DR Oh, JI Kim, MJ Seo, JG Kim, ST Ryu
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
282015
A 65-nm CMOS 6-bit 20 GS/s time-interleaved DAC with full-binary sub-DACs
SN Kim, WC Kim, MJ Seo, ST Ryu
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (9), 1154-1158, 2018
262018
Normalized-full-scale-referencing digital-domain linearity calibration for SAR ADC
DJ Chang, W Kim, MJ Seo, HK Hong, ST Ryu
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (2), 322-332, 2017
252017
A 7-bit two-step flash ADC with sample-and-hold sharing technique
DR Oh, MJ Seo, ST Ryu
IEEE Journal of Solid-State Circuits 57 (9), 2791-2801, 2022
242022
A 4.2 mW 10MHz BW 74.4 dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC
IH Jang, MJ Seo, MY Kim, JK Lee, SY Baek, SW Kwon, M Choi, HJ Ko, ...
2017 Symposium on VLSI Circuits, C34-C35, 2017
232017
A 40nm CMOS 12b 200MS/s single-amplifier dual-residue pipelined-SAR ADC
MJ Seo, YD Kim, JH Chung, ST Ryu
2019 Symposium on VLSI Circuits, C72-C73, 2019
222019
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18- m CMOS
MJ Seo, DH Jin, YD Kim, SI Hwang, JP Kim, ST Ryu
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (11), 3617-3627, 2018
192018
A single-supply CDAC-based buffer-embedding SAR ADC with skip-reset scheme having inherent chopping capability
MJ Seo, DH Jin, YD Kim, JP Kim, ST Ryu
IEEE Journal of Solid-State Circuits 55 (10), 2660-2669, 2020
182020
A 40-nm CMOS 7-b 32-GS/s SAR ADC with background channel mismatch calibration
DS Jo, MJ Seo, WC Kim, ST Ryu
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (4), 610-614, 2019
162019
A single-supply buffer-embedding SAR ADC with skip-reset having inherent chopping capability
MJ Seo, DH Jin, YD Kim, JP Kim, DJ Chang, WM Lim, JH Chung, CU Park, ...
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 189-192, 2019
82019
An 81.2 dB-SNDR dual-residue pipeline ADC with a 2nd-order noise-shaping interpolating SAR ADC
JH Chung, YD Kim, CU Park, KW Park, MJ Seo, ST Ryu
2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023
72023
A 65 nm 0.08-to-680 MHz low-power synthesizable MDLL with nested-delay cell and background static phase offset calibration
DJ Chang, MJ Seo, HK Hong, ST Ryu
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (3), 281-285, 2017
72017
Amorphous ITZO-based selector device for memristor crossbar array
KH Kim, MJ Seo, BC Jang
Micromachines 14 (3), 506, 2023
62023
A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF
YD Kim, JH Chung, KE Lozada, CU Park, KW Park, KH Song, YH Moon, ...
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024
52024
Analog-to-digital converter
J Kim, ST Ryu, MJ Seo
US Patent 10,931,298, 2021
52021
A 1.5-MHz BW 81.2-dB SNDR dual-residue pipeline ADC with a fully dynamic noise-shaping interpolating-SAR ADC
JH Chung, YD Kim, CU Park, KW Park, DR Oh, MJ Seo, ST Ryu
IEEE Journal of Solid-State Circuits 59 (8), 2481-2491, 2024
42024
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