Takip et
Hóngyè Huáng
Hóngyè Huáng
Diğer adlarHongye Huang
Tokyo Institute of Technology
ssc.pe.titech.ac.jp üzerinde doğrulanmış e-posta adresine sahip - Ana Sayfa
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
A 28-GHz CMOS phased-array transceiver based on LO phase-shifting architecture with gain invariant phase tuning for 5G new radio
J Pang, R Wu, Y Wang, M Dome, H Kato, H Huang, AT Narayanan, H Liu, ...
IEEE Journal of Solid-State Circuits 54 (5), 1228-1242, 2019
2062019
A 28-GHz CMOS phased-array beamformer utilizing neutralized bi-directional technique supporting dual-polarized MIMO for 5G NR
J Pang, Z Li, R Kubozoe, X Luo, R Wu, Y Wang, D You, AA Fadila, ...
IEEE Journal of Solid-State Circuits 55 (9), 2371-2386, 2020
2012020
A 265- W Fractional- Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65 …
H Liu, Z Sun, H Huang, W Deng, T Siriburanon, J Pang, Y Wang, R Wu, ...
IEEE Journal of Solid-State Circuits 54 (12), 3478-3492, 2019
752019
A CMOS dual-polarized phased-array beamformer utilizing cross-polarization leakage cancellation for 5G MIMO systems
J Pang, Z Li, X Luo, J Alvin, R Saengchan, AA Fadila, K Yanagisawa, ...
IEEE Journal of Solid-State Circuits 56 (4), 1310-1326, 2021
702021
An ADPLL-centric bluetooth low-energy transceiver with 2.3 mW interference-tolerant hybrid-loop receiver and 2.9 mW single-point polar transmitter in 65nm CMOS
H Liu, Z Sun, D Tang, H Huang, T Kaneko, W Deng, R Wu, K Okada, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 444-446, 2018
672018
A DPLL-centric Bluetooth low-energy transceiver with a 2.3-mW interference-tolerant hybrid-loop receiver in 65-nm CMOS
H Liu, Z Sun, D Tang, H Huang, T Kaneko, Z Chen, W Deng, R Wu, ...
IEEE Journal of Solid-State Circuits 53 (12), 3672-3687, 2018
452018
A 28GHz CMOS phased-array transceiver featuring gain invariance based on LO phase shifting architecture with 0.1-degree beam-steering resolution for 5G new radio
J Pang, R Wu, Y Wang, M Dome, H Kato, H Huang, AT Narayanan, H Liu, ...
2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 56-59, 2018
452018
A fully-synthesizable fractional-N injection-locked PLL for digital clocking with triangle/sawtooth spread-spectrum modulation capability in 5-nm CMOS
B Liu, Y Zhang, J Qiu, H Huang, Z Sun, D Xu, H Zhang, Y Wang, J Pang, ...
IEEE Solid-State Circuits Letters 3, 34-37, 2020
292020
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth
J Qiu, Z Sun, B Liu, W Wang, D Xu, H Herdian, H Huang, Y Zhang, ...
IEEE Journal of Solid-State Circuits 56 (12), 3741-3755, 2021
262021
A fast-beam-switching 28-GHz phased-array transceiver supporting cross-polarization leakage self-cancellation
J Pang, Z Li, X Luo, J Alvin, K Yanagisawa, Y Zhang, Z Chen, Z Huang, ...
2021 Symposium on VLSI Circuits, 1-2, 2021
182021
A 28-GHz CMOS phased-array beamformer supporting dual-polarized MIMO with cross-polarization leakage cancellation
J Pang, Z Li, X Luo, J Alvin, R Saengchan, AA Fadila, K Yanagisawa, ...
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
182020
A 0.85mm2BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver
Z Sun, H Liu, D Tang, H Huang, T Kaneko, R Wu, W Deng, K Okada
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018
182018
A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch
Z Sun, H Liu, H Huang, D Tang, D Xu, T Kaneko, Z Li, J Pang, R Wu, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (1), 196-209, 2020
142020
10.3 A 7GHz DIGITAL PLL with cascaded fractional divider and pseudo-differential DTC achieving-62.1 dBc fractional spur and 143.7 fs integrated jitter
D Xu, Z Liu, Y Kuai, H Huang, Y Zhang, Z Sun, B Liu, W Wang, Y Xiong, ...
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 192-194, 2024
132024
A 6.5-to-8GHz cascaded dual-fractional-N digital PLL achieving-63.7 dBc fractional spurs with 50MHz reference
D Xu, Y Zhang, H Huang, Z Sun, B Liu, AA Fadila, J Qiu, Z Liu, W Wang, ...
2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023
122023
A 28ghz cmos differential bi-directional amplifier for 5g nr
Z Li, J Pang, R Kubozoe, X Luo, R Wu, Y Wang, D You, AA Fadila, J Alvin, ...
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 5-6, 2020
122020
A 32kHz-reference 2.4 GHz fractional-N nonuniform oversampling PLL with gain-boosted PD and loop-gain calibration
J Qiu, W Wang, Z Sun, B Liu, Y Zhang, D Xu, H Huang, AA Fadila, Z Liu, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 80-82, 2023
82023
A fully synthesizable DPLL with background gain mismatch calibrated feedforward phase noise cancellation path
W Madany, Y Zhang, AA Fadila, H Huang, J Qiu, A Shirane, K Okada
ESSCIRC 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC …, 2023
32023
A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration
Z Sun, D Xu, J Qiu, Z Liu, Y Zhang, H Huang, H Liu, B Liu, Z Li, J Pang, ...
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021
32021
A 78 fs RMS jitter injection-locked clock multiplier using transformer-based ultra-low-power VCO
Z Sun, H Liu, D Xu, H Huang, B Liu, Z Li, J Pang, T Someya, A Shirane
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019
32019
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