| μBrain: An event-driven and fully synthesizable architecture for spiking neural networks J Stuijt, M Sifalakis, A Yousefzadeh, F Corradi Frontiers in neuroscience 15, 664208, 2021 | 138 | 2021 |
| On practical issues for stochastic STDP hardware with 1-bit synaptic weights A Yousefzadeh, E Stromatias, M Soto, T Serrano-Gotarredona, ... Frontiers in neuroscience 12, 665, 2018 | 76 | 2018 |
| Hardware implementation of convolutional STDP for on-line visual feature learning A Yousefzadeh, T Masquelier, T Serrano-Gotarredona, ... 2017 IEEE international symposium on circuits and systems (ISCAS), 1-4, 2017 | 51 | 2017 |
| On multiple AER handshaking channels over high-speed bit-serial bidirectional LVDS links with flow-control and clock-correction on commercial FPGAs for scalable neuromorphic … A Yousefzadeh, M Jabłoński, T Iakymchuk, A Linares-Barranco, A Rosado, ... IEEE transactions on biomedical circuits and systems 11 (5), 1133-1147, 2017 | 36 | 2017 |
| Tutorial on memristor-based computing for smart edge applications A Gebregiorgis, A Singh, A Yousefzadeh, D Wouters, R Bishnoi, ... Memories-Materials, Devices, Circuits and Systems 4, 100025, 2023 | 32 | 2023 |
| Asynchronous spiking neurons, the natural key to exploit temporal sparsity A Yousefzadeh, MA Khoei, S Hosseini, P Holanda, S Leroux, O Moreira, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (4 …, 2019 | 32 | 2019 |
| Active perception with dynamic vision sensors. Minimum saccades with optimum recognition A Yousefzadeh, G Orchard, T Serrano-Gotarredona, B Linares-Barranco IEEE transactions on biomedical circuits and systems 12 (4), 927-939, 2018 | 31 | 2018 |
| Sparnet: Sparse asynchronous neural network execution for energy efficient inference MA Khoei, A Yousefzadeh, A Pourtaherian, O Moreira, J Tapson 2020 2nd IEEE International Conference on Artificial Intelligence Circuits …, 2020 | 30 | 2020 |
| NeuronFlow: a neuromorphic processor architecture for live AI applications O Moreira, A Yousefzadeh, F Chersi, G Cinserin, RJ Zwartenkot, A Kapoor, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 840-845, 2020 | 30 | 2020 |
| Conversion of synchronous artificial neural network to asynchronous spiking neural network using sigma-delta quantization A Yousefzadeh, S Hosseini, P Holanda, S Leroux, T Werner, ... 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 29 | 2019 |
| Neurobench: Advancing neuromorphic computing through collaborative, fair and representative benchmarking J Yik, SH Ahmed, Z Ahmed, B Anderson, AG Andreou, C Bartolozzi, ... arXiv 2023, 2304.04640 v2, 2023 | 26 | 2023 |
| Fast pipeline 128× 128 pixel spiking convolution core for event-driven vision processing in FPGAs A Yousefzadeh, T Serrano-Gotarredona, B Linares-Barranco 2015 International conference on event-based control, communication, and …, 2015 | 24 | 2015 |
| Neuronflow: A hybrid neuromorphic–dataflow processor architecture for ai workloads O Moreira, A Yousefzadeh, F Chersi, A Kapoor, RJ Zwartenkot, P Qiao, ... 2020 2nd IEEE International Conference on Artificial Intelligence Circuits …, 2020 | 23 | 2020 |
| SENeCA: Scalable energy-efficient neuromorphic computer architecture A Yousefzadeh, GJ Van Schaik, M Tahghighi, P Detterer, S Traferro, ... 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 22 | 2022 |
| The neurobench framework for benchmarking neuromorphic computing algorithms and systems J Yik, K Van den Berghe, D den Blanken, Y Bouhadjar, M Fabre, ... Nature Communications 16 (1), 1545, 2025 | 21 | 2025 |
| Seneca: building a fully digital neuromorphic processor, design trade-offs and challenges G Tang, K Vadivel, Y Xu, R Bilgic, K Shidqi, P Detterer, S Traferro, ... Frontiers in Neuroscience 17, 1187252, 2023 | 19 | 2023 |
| Hybrid neural network, an efficient low-power digital hardware implementation of event-based artificial neural network A Yousefzadeh, G Orchard, E Stromatias, T Serrano-Gotarredona, ... 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 18 | 2018 |
| Fast predictive handshaking in synchronous FPGAs for fully asynchronous multisymbol chip links: Application to SpiNNaker 2-of-7 links A Yousefzadeh, LA Plana, S Temple, T Serrano-Gotarredona, SB Furber, ... IEEE Transactions on Circuits and Systems II: Express Briefs 63 (8), 763-767, 2016 | 14 | 2016 |
| Empirical study on the efficiency of spiking neural networks with axonal delays, and algorithm-hardware benchmarking A Patiño-Saucedo, A Yousefzadeh, G Tang, F Corradi, ... 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 13 | 2023 |
| Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design G Tang, A Safa, K Shidqi, P Detterer, S Traferro, M Konijnenburg, ... 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 13 | 2023 |
Bernabe Linares-BarrancoInstituto de Microelectrónica de Sevilla, IMSE-CNM, Universidad de Sevilla, CSICimse-cnm.csic.es üzerinde doğrulanmış e-posta adresine sahip
