Takip et
Rajeev Balasubramonian
Rajeev Balasubramonian
Professor, School of Computing, University of Utah
cs.utah.edu üzerinde doğrulanmış e-posta adresine sahip - Ana Sayfa
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars
A Shafiee, A Nag, N Muralimanohar, R Balasubramonian, JP Strachan, ...
Proceedings of the 43rd International Symposium on Computer Architecture, 14-26, 2016
23002016
CACTI 6.0: A tool to model large caches
N Muralimanohar, R Balasubramonian, NP Jouppi
HP Laboratories, 22-31, 2009
13152009
Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0
N Muralimanohar, R Balasubramonian, N Jouppi
Proceedings of the 40th Annual IEEE/ACM International Symposium on …, 2007
8372007
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
G Semeraro, G Magklis, R Balasubramonian, DH Albonesi, S Dwarkadas, ...
Proceedings Eighth International Symposium on High Performance Computer …, 2002
5752002
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
R Balasubramonian, D Albonesi, A Buyuktosunoglu, S Dwarkadas
Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000
5712000
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories
R Balasubramonian, AB Kahng, N Muralimanohar, A Shafiee, V Srinivas
ACM Transactions on Architecture and Code Optimization (TACO) 14 (2), 14, 2017
4952017
Overcoming the challenges of crossbar resistive memory architectures
C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
4232015
Rethinking DRAM design and organization for energy-constrained multi-cores
AN Udipi, N Muralimanohar, N Chatterjee, R Balasubramonian, A Davis, ...
Proceedings of the 37th annual international symposium on Computer …, 2010
3612010
NDC: Analyzing the impact of 3D-stacked memory+ logic devices on MapReduce workloads
SH Pugsley, J Jestes, H Zhang, R Balasubramonian, V Srinivasan, ...
Performance Analysis of Systems and Software (ISPASS), 2014 IEEE …, 2014
3522014
Near-Data Processing: Insights from a MICRO-46 Workshop
R Balasubramonian, J Chang, T Manning, JH Moreno, R Murphy, R Nair, ...
Micro, IEEE 34 (4), 36-42, 2014
3172014
Reducing the complexity of the register file in dynamic superscalar processors
R Balasubramonian, S Dwarkadas, DH Albonesi
Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International …, 2001
3172001
Micro-pages: increasing DRAM efficiency with locality-aware data placement
K Sudan, N Chatterjee, D Nellans, M Awasthi, R Balasubramonian, ...
ACM SIGARCH Computer Architecture News 38 (1), 219-230, 2010
3082010
Leveraging 3D technology for improved reliability
N Madan, R Balasubramonian
Proceedings of the 40th Annual IEEE/ACM International Symposium on …, 2007
2932007
Multiple clock domain microprocessor
D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ...
US Patent 7,089,443, 2006
250*2006
Multiple clock domain microprocessor
D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ...
US Patent 7,089,443, 2006
250*2006
Multiple clock domain microprocessor
D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ...
US Patent 7,739,537, 2010
2262010
Efficiently prefetching complex address patterns
M Shevgoor, S Koladiya, R Balasubramonian, C Wilkerson, SH Pugsley, ...
Proceedings of the 48th International Symposium on Microarchitecture, 141-152, 2015
2182015
Dynamically tuning processor resources with adaptive processing
DH Albonesi, R Balasubramonian, SG Dropsbo, S Dwarkadas, ...
Computer 36 (12), 49-58, 2003
2152003
USIMM: the Utah SImulated Memory Module
N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ...
Technical report, University of Utah, 2012. UUCS-12-002, 2012
2002012
CHOP: Adaptive filter-based dram caching for CMP server platforms
X Jiang, N Madan, L Zhao, M Upton, R Iyer, S Makineni, D Newell, ...
High Performance Computer Architecture (HPCA), 2010 IEEE 16th International …, 2010
1992010
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