Kamu erişimi zorunlu olan makaleler - Rahul ShresthaDaha fazla bilgi edinin
Hiçbir yerde sunulmuyor: 9
Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes
A Verma, R Shrestha
IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, 2022
Zorunlu olanlar: Department of Science & Technology, India
A new partially-parallel VLSI-architecture of quasi-cyclic LDPC decoder for 5G new-radio
A Verma, R Shrestha
2020 33rd International Conference on VLSI Design and 2020 19th …, 2020
Zorunlu olanlar: Department of Science & Technology, India
PGMA: an algorithmic approach for multi-objective hardware software partitioning
N Govil, R Shrestha, SR Chowdhury
Microprocessors and Microsystems 54, 83-96, 2017
Zorunlu olanlar: Department of Science & Technology, India
Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture
A Verma, R Shrestha
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, 2021
Zorunlu olanlar: Department of Science & Technology, India
VLSI-architecture of radix-2/4/8 SISO decoder for turbo decoding at multiple data-rates
R Shrestha, A Sharma
2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018
Zorunlu olanlar: Department of Science & Technology, India
VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing
EJT Pereira, DA Guimarães, R Shrestha
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, 2024
Zorunlu olanlar: Government of Spain
High-Throughput and Hardware-Efficient ASIC-Chip Fabrication of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications
A Verma, R Shrestha
IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS I: REGULAR PAPERS, 2024
Zorunlu olanlar: Department of Science & Technology, India
A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications
R Shrestha
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020
Zorunlu olanlar: Department of Science & Technology, India
Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices
R Shrestha, A Sharma
International Symposium on VLSI Design and Test, 37-48, 2018
Zorunlu olanlar: Department of Science & Technology, India
Bir yerde sunuluyor: 1
A new VLSI architecture of next-generation QC-LDPC decoder for 5G new-radio wireless-communication standard
A Verma, R Shrestha
2020 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2020
Zorunlu olanlar: Department of Science & Technology, India
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