| Contact resistance reduction by new barrier stack process D Yue, S Grunow, SSP Rao, NM Russell, M Leavy US Patent 7,256,121, 2007 | 190 | 2007 |
| MIM capacitors and methods for fabricating same SSP Rao, AM Haider, K Taylor, E Burke US Patent 6,803,641, 2004 | 102 | 2004 |
| Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess SP Rao, S Grunow, N Russell US Patent App. 10/903,597, 2006 | 96 | 2006 |
| Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales J Bai, D Wang, S Nam, H Peng, R Bruce, L Gignac, M Brink, E Kratschmer, ... Nanoscale 6 (15), 8900-8906, 2014 | 87 | 2014 |
| GaAs on Si epitaxy by aspect ratio trapping: Analysis and reduction of defects propagating along the trench direction T Orzali, A Vert, B O'Brien, JL Herman, S Vivekanand, RJW Hill, Z Karim, ... Journal of Applied Physics 118 (10), 2015 | 70 | 2015 |
| The use of EUV lithography to produce demonstration devices B LaFontaine, Y Deng, RH Kim, HJ Levinson, S McGowan, ... Emerging Lithographic Technologies XII 6921, 212-221, 2008 | 69 | 2008 |
| Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules C Wang, SW Nam, JM Cotte, CV Jahnes, E Colgan, RL Bruce, M Brink, ... Nature Communications 8, 2017 | 63 | 2017 |
| Revisiting the theory of ferroelectric negative capacitance K Majumdar, S Datta, SP Rao IEEE Transactions on Electron Devices 63 (5), 2043-2049, 2016 | 56 | 2016 |
| Method to improve inductance with a high-permeability slotted plate core in an integrated circuit KD Brennan, SSP Rao, B Williams US Patent 7,436,281, 2008 | 47 | 2008 |
| Optimization of photoluminescence from W centers in silicon-on-insulator SM Buckley, AN Tait, G Moody, B Primavera, S Olson, J Herman, ... Optics Express 28 (11), 16057-16072, 2020 | 43 | 2020 |
| Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode DL Crenshaw, BL Williams, A Tsao, H Shichijo, SSP Rao, KD Brennan, ... US Patent 7,250,334, 2007 | 39 | 2007 |
| Epitaxial growth of GaSb and InAs fins on 300 mm Si (001) by aspect ratio trapping T Orzali, A Vert, B O'Brian, JL Herman, S Vivekanand, SS Papa Rao, ... Journal of Applied Physics 120 (8), 085308, 2016 | 37 | 2016 |
| 10 nm nominal channel length MoS2 FETs with EOT 2.5 nm and 0.52 mA/µm drain current L Yang, RTP Lee, SSP Rao, W Tsai, PD Ye 2015 73rd Annual Device Research Conference (DRC), 237-238, 2015 | 37 | 2015 |
| Capacitor integration at top-metal level with a protection layer for the copper surface SSP Rao, TA Rost, E Burke US Patent 7,015,093, 2006 | 33 | 2006 |
| Systems and methods that selectively modify liner induced stress T Tsui, SSP Rao, H Bu, R Kraft US Patent 7,939,400, 2011 | 31 | 2011 |
| Processing and moisture effects on TDDB for Cu/ULK BEOL structures EG Liniger, TM Shaw, SA Cohen, PK Leung, SM Gates, G Bonilla, ... Microelectronic Engineering 92, 130-133, 2012 | 29 | 2012 |
| Systems and methods that selectively modify liner induced stress TY Tsui, SSP Rao, H Bu, R Kraft US Patent 7,442,597, 2008 | 29 | 2008 |
| Partial plate anneal plate process for deposition of conductive fill material M Leavy, S Grunow, SSP Rao, NM Russell US Patent 7,148,140, 2006 | 29 | 2006 |
| Use of supercritical fluid for low effective dielectric constant metallization SS Papa Rao, S Grunow, PD Matz, TI Incorporated US Patent 7,179,747, 2007 | 27 | 2007 |
| Integration of pore sealing liner into dual-damascene methods and devices ER Engbrecht, SSP Rao, SK Ajmera, S Grunow US Patent 7,338,893, 2008 | 26 | 2008 |