| Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance H Amrouch, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan IEEE Access 6, 52754-52765, 2018 | 87 | 2018 |
| Compact modeling of drain current, charges, and capacitances in long-channel gate-all-around negative capacitance MFIS transistor AD Gaidhane, G Pahwa, A Verma, YS Chauhan IEEE Transactions on Electron Devices 65 (5), 2024-2032, 2018 | 77 | 2018 |
| Impact of variability on processor performance in negative capacitance finfet technology H Amrouch, G Pahwa, AD Gaidhane, CK Dabhi, F Klemme, O Prakash, ... IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 3127-3137, 2020 | 66 | 2020 |
| Unveiling the impact of IR-drop on performance gain in NCFET-based processors H Amrouch, S Salamin, G Pahwa, AD Gaidhane, J Henkel, YS Chauhan IEEE Transactions on Electron Devices 66 (7), 3215-3223, 2019 | 30 | 2019 |
| Gate-induced drain leakage in negative capacitance FinFETs AD Gaidhane, G Pahwa, A Verma, YS Chauhan IEEE Transactions on Electron Devices 67 (3), 802-809, 2020 | 26 | 2020 |
| A computationally efficient compact model for ferroelectric switching with asymmetric nonperiodic input signals AD Gaidhane, R Dangi, S Sahay, A Verma, YS Chauhan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 21 | 2022 |
| Ferroelectric FDSOI FET modeling for memory and logic applications S Chatterjee, S Kumar, A Gaidhane, CK Dabhi, YS Chauhan, H Amrouch Solid-State Electronics 200, 108554, 2023 | 19 | 2023 |
| Compact modeling of surface potential, drain current and terminal charges in negative capacitance nanosheet FET including quasi-ballistic transport AD Gaidhane, G Pahwa, A Dasgupta, A Verma, YS Chauhan IEEE Journal of the Electron Devices Society 8, 1168-1176, 2020 | 17 | 2020 |
| Ferroelectric FET-based implementation of Fitzhugh-Nagumo neuron model D Rajasekharan, A Gaidhane, AR Trivedi, YS Chauhan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 13 | 2021 |
| Compact modeling of drain current in double gate negative capacitance MFIS transistor AD Gaidhane, G Pahwa, A Verma, YS Chauhan 2018 4th IEEE International Conference on Emerging Electronics (ICEE), 1-5, 2018 | 11 | 2018 |
| Assessing negative-capacitance drain-extended technology for high-voltage switching and analog applications G Pahwa, AD Gaidhane, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 68 (2), 679-687, 2020 | 10 | 2020 |
| Modeling of inner fringing charges and short channel effects in negative capacitance MFIS transistor AD Gaidhane, G Pahwa, A Verma, YS Chauhan 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 282-284, 2019 | 9 | 2019 |
| Graph-based compact model (GCM) for efficient transistor parameter extraction: A machine learning approach on 12 nm FinFETs Z Yang, AD Gaidhane, K Anderson, G Workman, Y Cao IEEE Transactions on Electron Devices 71 (1), 254-262, 2023 | 8 | 2023 |
| Study of multi-domain switching dynamics in negative capacitance FET using SPICE model AD Gaidhane, A Verma, YS Chauhan Microelectronics Journal 115, 105186, 2021 | 8 | 2021 |
| Modeling of multi-domain switching in ferroelectric materials: Application to negative capacitance FETs A Dasgupta, P Rastogi, D Saha, A Gaidhane, A Agarwal, YS Chauhan 2018 IEEE International Electron Devices Meeting (IEDM), 9.2. 1-9.2. 4, 2018 | 8 | 2018 |
| Physics-constrained graph modeling for building thermal dynamics Z Yang, AD Gaidhane, J Drgoňa, V Chandan, MM Halappanavar, F Liu, ... Energy and AI 16, 100346, 2024 | 6 | 2024 |
| Design exploration of 14 nm FinFET for energy-efficient cryogenic computing AD Gaidhane, R Saligram, W Chakraborty, S Datta, A Raychowdhury, ... IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 9 …, 2023 | 6 | 2023 |
| Ferroelectric FET-based time-mode multiply-accumulate accelerator: Design and analysis M Rafiq, T Kaur, A Gaidhane, YS Chauhan, S Sahay IEEE Transactions on Electron Devices 70 (12), 6613-6621, 2023 | 6 | 2023 |
| A computationally efficient compact model for ferroelectric FinFETs switching with asymmetric non-periodic input signals S Sahay, A Gaidhane, YS Chauhan, R Dangi, A Verma Authorea Preprints, 2023 | 5 | 2023 |
| Compact modeling of negative capacitance nanosheet FET including quasi-ballistic transport AD Gaidhane, G Pahwa, A Dasgupta, A Verma, YS Chauhan 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020 | 5 | 2020 |
Yogesh S. ChauhanFellow IEEE, FNAE, Professor-IIT KanpurVerifierad e-postadress på iitk.ac.in