Članki z zahtevami za javni dostop - Vincenzo RanaVeč o tem
Ni na voljo nikjer: 2
Time of arrival cumulative probability in public transportation travel assistance
A Pagani, F Bruschi, V Rana
2017 IEEE 20th International Conference on Intelligent Transportation …, 2017
Zahteve: Government of Italy
User context estimation for public travel assistance and intelligent service scheduling
A Pagani, F Bruschi, V Rana, M Restelli
2017 IEEE 20th International Conference on Intelligent Transportation …, 2017
Zahteve: Government of Italy
Na voljo nekje: 13
A mapping flow for dynamically reconfigurable multi-core system-on-chip design
I Beretta, V Rana, D Atienza, D Sciuto
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
Zahteve: Swiss National Science Foundation
Partial dynamic reconfiguration in a multi-fpga clustered architecture based on linux
V Rana, M Santambrogio, D Sciuto, B Kettelhoit, M Koester, M Porrmann, ...
2007 IEEE International Parallel and Distributed Processing Symposium, 1-8, 2007
Zahteve: German Research Foundation
A real-time information system for public transport in case of delays and service disruptions
M Bruglieri, F Bruschi, A Colorni, A Luè, R Nocerino, V Rana
Transportation Research Procedia 10, 493-502, 2015
Zahteve: Government of Italy
A reconfigurable network-on-chip architecture for optimal multi-processor SoC communication
V Rana, D Atienza, MD Santambrogio, D Sciuto, G De Micheli
VLSI-SoC: Design Methodologies for SoC and SiP: 16th IFIP WG 10.5/IEEE …, 2010
Zahteve: Swiss National Science Foundation
A hybrid mapping-scheduling technique for dynamically reconfigurable hardware
JA Clemente, V Rana, D Sciuto, I Beretta, D Atienza
2011 21st International Conference on Field Programmable Logic and …, 2011
Zahteve: Swiss National Science Foundation, Government of Spain
A mapping-scheduling algorithm for hardware acceleration on reconfigurable platforms
JA Clemente, I Beretta, V Rana, D Atienza, D Sciuto
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-27, 2014
Zahteve: Swiss National Science Foundation, Government of Spain
Model-based design for wireless body sensor network nodes
I Beretta, F Rincon, N Khaled, PR Grassi, V Rana, D Atienza, D Sciuto
2012 13th Latin American Test Workshop (LATW), 1-6, 2012
Zahteve: Swiss National Science Foundation
Design exploration of energy-performance trade-offs for wireless sensor networks
I Beretta, F Rincon, N Khaled, PR Grassi, V Rana, D Atienza
Proceedings of the 49th Annual Design Automation Conference, 1043-1048, 2012
Zahteve: Swiss National Science Foundation, Government of Spain
Efficient hardware design of iterative stencil loops
V Rana, I Beretta, F Bruschi, AA Nacci, D Atienza, D Sciuto
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
Zahteve: Swiss National Science Foundation
Run-time mapping of applications on FPGA-based reconfigurable systems
I Beretta, V Rana, D Atienza, D Sciuto
2010 IEEE International Symposium on Circuits and Systems (ISCAS), 3329-3332, 2010
Zahteve: Swiss National Science Foundation
Island-based adaptable embedded system design
I Beretta, V Rana, D Atienza, D Sciuto
IEEE Embedded Systems Letters 3 (2), 53-57, 2011
Zahteve: Swiss National Science Foundation
Parallelizing the Chambolle algorithm for performance-optimized mapping on FPGA devices
I Beretta, V Rana, A Akin, AA Nacci, D Sciuto, D Atienza
ACM Transactions on Embedded Computing Systems (TECS) 15 (3), 1-27, 2016
Zahteve: Swiss National Science Foundation
A high-performance parallel implementation of the Chambolle algorithm
A Akin, I Beretta, AA Nacci, V Rana, MD Santambrogio, D Atienza
2011 Design, Automation & Test in Europe, 1-6, 2011
Zahteve: Swiss National Science Foundation
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