| A 200-MHz 64-b dual-issue CMOS microprocessor DW Dobberpuhl, RT Witek, R Allmon, R Anglin, D Bertucci, S Britton, ... IEEE Journal of Solid-State Circuits 27 (11), 1555-1567, 1992 | 691 | 1992 |
| A 600 MHz superscalar RISC microprocessor with out-of-order execution BA Gieseke, RL Allmon, DW Bailey, BJ Benschneider, SM Britton, ... 1997 IEEE International Solids-State Circuits Conference. Digest of …, 1997 | 265 | 1997 |
| Alpha processors: A history of power issues and a look to the future K Wilcox, S Manne Cool-Chips Tutorial, 1999 | 98 | 1999 |
| Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU T Fischer, S Arekapudi, E Busta, C Dietz, M Golden, S Hilker, A Horiuchi, ... 2011 IEEE International Solid-State Circuits Conference, 78-80, 2011 | 66 | 2011 |
| A 200-MHz 64-bit dual-issue CMOS microprocessor DW Dobberpuhl, RT Witek, R Allmon, R Anglin, D Bertucci, S Britton, ... Digital Technical Journal 4, 35-35, 1993 | 48 | 1993 |
| Steamroller module and adaptive clocking system in 28 nm CMOS K Wilcox, R Cole, HR Fair III, K Gillespie, A Grenat, C Henrion, R Jotwani, ... IEEE Journal of Solid-State Circuits 50 (1), 24-34, 2014 | 47 | 2014 |
| Circuit implementation of a 600 MHz superscalar RISC microprocessor M Matson, D Bailey, S Bell, L Biro, S Butler, J Clouser, J Farrell, M Gowan, ... Proceedings International Conference on Computer Design. VLSI in Computers …, 1998 | 41 | 1998 |
| Carrizo: A high performance, energy efficient 28 nm APU B Munger, D Akeson, S Arekapudi, T Burd, HR Fair, J Farrell, D Johnson, ... IEEE Journal of Solid-State Circuits 51 (1), 105-116, 2015 | 24 | 2015 |
| 4.8 A 28nm x86 APU optimized for power and area efficiency K Wilcox, D Akeson, HR Fair, J Farrell, D Johnson, G Krishnan, H Mclntyre, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 21 | 2015 |
| 5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS K Gillespie, HR Fair, C Henrion, R Jotwani, S Kosonocky, RS Orefice, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 19 | 2014 |
| Design technology co-optimization: Tradeoffs for building the best processor K Wilcox, L Gentile, K Gillespie IEEE Solid-State Circuits Magazine 11 (4), 58-66, 2019 | 5 | 2019 |
| Through silicon via macro with dense layout for placement in an integrated circuit floorplan ME Griffith, AK Horiuchi, DA Clay, EW Busta, HJ Stanford, KE Wilcox, ... US Patent App. 17/854,516, 2024 | | 2024 |
