| Post-training piecewise linear quantization for deep neural networks J Fang, A Shafiee, H Abdel-Aziz, D Thorsley, G Georgiadis, JH Hassoun Computer Vision–ECCV 2020: 16th European Conference, Glasgow, UK, August 23 …, 2020 | 200 | 2020 |
| Learned token pruning for transformers S Kim, S Shen, D Thorsley, A Gholami, W Kwon, J Hassoun, K Keutzer Proceedings of the 28th ACM SIGKDD Conference on Knowledge Discovery and …, 2022 | 172 | 2022 |
| A fast post-training pruning framework for transformers W Kwon, S Kim, MW Mahoney, J Hassoun, K Keutzer, A Gholami Advances in Neural Information Processing Systems 35, 24101-24116, 2022 | 148 | 2022 |
| Delay lock loop with clock phase shifter JH Hassoun, FE Goetting, JD Logue US Patent 6,289,068, 2001 | 140 | 2001 |
| Sparsity-aware and re-configurable NPU architecture for Samsung flagship mobile SoC JW Jang, S Lee, D Kim, H Park, AS Ardestani, Y Choi, C Kim, Y Kim, H Yu, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 108 | 2021 |
| Programmable logic core adapter JM Arnold, RC Camarota, JH Hassoun, R Charle'R US Patent 6,744,274, 2004 | 81 | 2004 |
| SDRAM controller implemented in a PLD JH Hassoun US Patent 6,487,648, 2002 | 72 | 2002 |
| Precision trim circuit for delay lines FE Goetting, PG Hyland, JH Hassoun US Patent 6,204,710, 2001 | 57 | 2001 |
| Delay lock loop with clock phase shifter JH Hassoun, FE Goetting, JD Logue US Patent 6,587,534, 2003 | 51 | 2003 |
| Double data rate flip-flop SP Young, SM Menon, K Sodha, RA Carberry, JH Hassoun US Patent 6,525,565, 2003 | 43 | 2003 |
| Cache tag system for use with multiple processors including the most recently requested processor identification JH Hassoun, ML Ziegler, RD Odineal US Patent 5,737,757, 1998 | 42 | 1998 |
| Variable clock divider with selectable duty cycle JH Hassoun US Patent 6,061,418, 2000 | 34 | 2000 |
| Current mode interface circuitry for an IC test device JH Hassoun, JA Gasbarro US Patent 5,844,913, 1998 | 33 | 1998 |
| Forming linked lists using content addressable memory S Iacobovici, WR Bryg, JH Hassoun US Patent 5,995,967, 1999 | 30 | 1999 |
| Near-lossless post-training quantization of deep neural networks via a piecewise linear approximation J Fang, A Shafiee, H Abdel-Aziz, D Thorsley, G Georgiadis, J Hassoun arXiv preprint arXiv:2002.00104 10, 978-3, 2020 | 23 | 2020 |
| An elemental computing architecture for SD radio S Kelem, B Box, S Wasson, R Plunkett, J Hassoun, C Phillips Proc. Software Defined Radio Technical Conf. Product Exposition, 2007 | 21 | 2007 |
| Double data rate flip-flop SP Young, SM Menon, K Sodha, RA Carberry, JH Hassoun US Patent 6,777,980, 2004 | 20 | 2004 |
| Sait: Sparse vision transformers through adaptive token pruning L Li, D Thorsley, J Hassoun arXiv preprint arXiv:2210.05832, 2022 | 19 | 2022 |
| Mixed-precision NPU tile with depth-wise convolution I Ovsiannikov, AS Ardestani, HAA Abdelaziz, JH Hassoun US Patent 11,880,760, 2024 | 18 | 2024 |
| Griffin: Rethinking sparse optimization for deep learning architectures JH Shin, A Shafiee, A Pedram, H Abdel-Aziz, L Li, J Hassoun 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022 | 17 | 2022 |