| Junctionless multiple-gate transistors for analog applications RT Doria, MA Pavanello, RD Trevisoli, M de Souza, CW Lee, I Ferain, ... IEEE Transactions on Electron Devices 58 (8), 2511-2519, 2011 | 289 | 2011 |
| Threshold voltage in junctionless nanowire transistors RD Trevisoli, RT Doria, M de Souza, MA Pavanello Semiconductor Science and Technology 26 (10), 105009, 2011 | 133 | 2011 |
| Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors RD Trevisoli, RT Doria, M de Souza, S Das, I Ferain, MA Pavanello IEEE Transactions on Electron Devices 59 (12), 3510-3518, 2012 | 128 | 2012 |
| Cryogenic operation of junctionless nanowire transistors M de Souza, MA Pavanello, RD Trevisoli, RT Doria, JP Colinge IEEE Electron Device Letters 32 (10), 1322-1324, 2011 | 64 | 2011 |
| Impact of the Series Resistance in the IV Characteristics of Junctionless Nanowire Transistors and its Dependence on the Temperature RT Doria, RD Trevisoli, M de Souza, MA Pavanello Journal Integrated Circuits and Systems 7 (1), 121-129, 2012 | 63 | 2012 |
| A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors RD Trevisoli, RT Doria, M de Souza, MA Pavanello Solid-State Electronics 90, 12-17, 2013 | 57 | 2013 |
| Charge-based continuous model for long-channel symmetric double-gate junctionless transistors A Cerdeira, M Estrada, B Iniguez, RD Trevisoli, RT Doria, M de Souza, ... Solid-State Electronics 85, 59-63, 2013 | 47 | 2013 |
| Thermal and rheological behavior of diesel and methanol biodiesel blends RA Candeia, JCO Freitas, MAF Souza, MM Conceição, IMG Santos, ... Journal of thermal analysis and calorimetry 87, 653-656, 2007 | 45 | 2007 |
| The zero temperature coefficient in junctionless nanowire transistors R Doria Trevisoli, R Trevisoli Doria, M de Souza, S Das, I Ferain, ... Applied Physics Letters 101 (6), 2012 | 40 | 2012 |
| An explicit multi-exponential model for semiconductor junctions with series and shunt resistances D Lugo-Munoz, J Muci, A Ortiz-Conde, FJ Garcia-Sanchez, M De Souza, ... Microelectronics Reliability 51 (12), 2044-2048, 2011 | 40 | 2011 |
| Substrate bias influence on the operation of junctionless nanowire transistors R Trevisoli, RT Doria, M de Souza, MA Pavanello IEEE Transactions on Electron Devices 61 (5), 1575-1582, 2014 | 39 | 2014 |
| Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors M De Souza, D Flandre, MA Pavanello IEEE 2011 International SOI Conference, 1-2, 2011 | 33 | 2011 |
| Compact core model for symmetric double-gate junctionless transistors A Cerdeira, F Ávila, B Iñiguez, M De Souza, MA Pavanello, M Estrada Solid-State Electronics 94, 91-97, 2014 | 30 | 2014 |
| Thin-Film Lateral SOI PIN Diodes for Thermal Sensing Reaching the Cryogenic Regime M de Souza, B Rue, D Flandre, MA Pavanello Journal Integrated Circuits and Systems 5 (2), 160-167, 2010 | 30 | 2010 |
| Thermal analysis kinetics applied to flame retardant polycarbonate H Polli, L Pontes, M Souza, V Fernandes Jr, A Araujo Journal of thermal analysis and calorimetry 86 (2), 469-473, 2006 | 30 | 2006 |
| Analysis of the leakage current in junctionless nanowire transistors R Trevisoli, R Trevisoli Doria, M de Souza, M Antonio Pavanello Applied Physics Letters 103 (20), 2013 | 28 | 2013 |
| Thermal and kinetic study of statins: Simvastatin and lovastatin M Souza, M Conceição, M Silva, L Soledade, A Souza Journal of thermal analysis and calorimetry 87 (3), 859-863, 2007 | 28 | 2007 |
| On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration M de Souza, D Flandre, RT Doria, R Trevisoli, MA Pavanello Solid-State Electronics 117, 152-160, 2016 | 25 | 2016 |
| Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors R Trevisoli, RT Doria, M de Souza, S Barraud, M Vinet, MA Pavanello IEEE Transactions on Electron Devices 63 (2), 856-863, 2015 | 25 | 2015 |
| Junctionless nanowire transistors operation at temperatures down to 4.2 K R Trevisoli, M De Souza, RT Doria, V Kilchtyska, D Flandre, MA Pavanello Semiconductor Science and Technology 31 (11), 114001, 2016 | 23 | 2016 |
Marcelo Antonio PavanelloFull Professor, Department of Electrical Engineering, Centro Universitário da FEIПодтвержден адрес электронной почты в домене fei.edu.br
