| A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors WH Chen, KX Li, WY Lin, KH Hsu, PY Li, CH Yang, CX Xue, EY Yang, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 494-496, 2018 | 351 | 2018 |
| 24.1 A 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 388-390, 2019 | 282 | 2019 |
| 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019 | 246 | 2019 |
| 15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices CX Xue, TY Huang, JS Liu, TW Chang, HY Kao, JH Wang, TW Liu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 244-246, 2020 | 236 | 2020 |
| CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors WH Chen, C Dou, KX Li, WY Lin, PY Li, JH Huang, JH Wang, WC Wei, ... Nature Electronics 2 (9), 420-428, 2019 | 214 | 2019 |
| 15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... 2020 IEEE international solid-state circuits conference-(ISSCC), 246-248, 2020 | 213 | 2020 |
| Optimizing NAND flash-based SSDs via retention relaxation RS Liu, CL Yang, W Wu 10th USENIX Conference on File and Storage Technologies (FAST), 2012 | 194 | 2012 |
| A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... IEEE Journal of Solid-State Circuits 55 (1), 189-202, 2019 | 193 | 2019 |
| 15.2 A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 240-242, 2020 | 175 | 2020 |
| 16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices CX Xue, JM Hung, HY Kao, YH Huang, SP Huang, FC Chang, P Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 245-247, 2021 | 169 | 2021 |
| 16.3 A 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hung, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 250-252, 2021 | 164 | 2021 |
| NVM Duet: Unified working memory and persistent store architecture RS Liu, DY Shen, CL Yang, SC Yu, CYM Wang 19th ACM International Conference on Architectural Support for Programming …, 2014 | 141 | 2014 |
| A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices CX Xue, YC Chiu, TW Liu, TY Huang, JS Liu, TW Chang, HY Kao, ... Nature Electronics 4 (1), 81-90, 2021 | 125 | 2021 |
| A 28nm 1Mb time-domain computing-in-memory 6T-SRAM macro with a 6.6 ns latency, 1241GOPS and 37.01 TOPS/W for 8b-MAC operations for edge-AI devices PC Wu, JW Su, YL Chung, LY Hong, JS Ren, FC Chang, Y Wu, HY Chen, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 109 | 2022 |
| Embedded 1-Mb ReRAM-based computing-in-memory macro with multibit input and weight for CNN-based AI edge processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... IEEE Journal of Solid-State Circuits 55 (1), 203-215, 2019 | 94 | 2019 |
| A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... IEEE Journal of Solid-State Circuits 56 (9), 2817-2831, 2021 | 88 | 2021 |
| An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing-in-memory macro using time-space-readout with 1286.4-21.6 TOPS/W for edge-AI devices JM Hung, YH Huang, SP Huang, FC Chang, TH Wen, CI Su, WS Khwa, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 83 | 2022 |
| A 4-Kb 1-to-8-bit configurable 6T SRAM-based computation-in-memory unit-macro for CNN-based AI edge processors YC Chiu, Z Zhang, JJ Chen, X Si, R Liu, YN Tu, JW Su, WH Huang, ... IEEE Journal of Solid-State Circuits 55 (10), 2790-2801, 2020 | 82 | 2020 |
| A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices JM Hung, CX Xue, HY Kao, YH Huang, FC Chang, SP Huang, TW Liu, ... Nature Electronics 4 (12), 921-930, 2021 | 75 | 2021 |
| A 0.5-V real-time computational CMOS image sensor with programmable kernel for feature extraction TH Hsu, YR Chen, RS Liu, CC Lo, KT Tang, MF Chang, CC Hsieh IEEE Journal of Solid-State Circuits 56 (5), 1588-1596, 2020 | 72 | 2020 |
