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| Memristive technologies for data storage, computation, encryption, and radio-frequency communication M Lanza, A Sebastian, WD Lu, M Le Gallo, MF Chang, D Akinwande, ... Science 376 (6597), eabj9979, 2022 | 398 | 2022 |
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| A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498, 2018 | 268 | 2018 |
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| 15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices CX Xue, TY Huang, JS Liu, TW Chang, HY Kao, JH Wang, TW Liu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 244-246, 2020 | 236 | 2020 |
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| 15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... 2020 IEEE international solid-state circuits conference-(ISSCC), 246-248, 2020 | 213 | 2020 |
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| Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical-stacked resistive memory (memristor) devices for low power mobile applications PF Chiu, MF Chang, CW Wu, CH Chuang, SS Sheu, YS Chen, MJ Tsai IEEE Journal of Solid-State Circuits 47 (6), 1483-1496, 2012 | 189 | 2012 |
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| 15.2 A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 240-242, 2020 | 175 | 2020 |
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| 16.3 A 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hung, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 250-252, 2021 | 164 | 2021 |
Kea-Tiong TangNational Tsing Hua UniversityПодтвержден адрес электронной почты в домене ee.nthu.edu.tw
