| A new design of the CMOS full adder N Zhuang, H Wu IEEE journal of solid-state circuits 27 (5), 840-844, 1992 | 463 | 1992 |
| Improved variable ordering of BDDS with novel genetic algorithm N Zhuang, MST Benten, PYK Cheung 1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996 | 48 | 1996 |
| A framework for developing parametrised FPGA libraries W Luk, S Guo, N Shirazi, N Zhuang Field-Programmable Logic Smart Applications, New Paradigms and Compilers …, 1996 | 43 | 1996 |
| Generalized partially-mixed-polarity Reed-Muller expansion and its fast computation H Wu, MA Perkowski, X Zeng, N Zhuang IEEE transactions on computers 45 (9), 1084-1088, 1996 | 36 | 1996 |
| Minimisation of multioutput Reed-Muller binary decision diagrams using hybrid genetic algorithm AEA Almaini, N Zhuang, F Bourset Electronics Letters 31 (20), 1722-1723, 1995 | 26 | 1995 |
| Novel ternary JKL flip-flop N Zhuang, H Wu Electronics Letters 26 (15), 1145-1146, 1990 | 20 | 1990 |
| Using genetic algorithms for the variable ordering of Reed-Muller binary decision diagrams AEA Almaini, N Zhuang Microelectronics journal 26 (5), 471-480, 1995 | 19 | 1995 |
| Fast synthesis for ternary Reed-Muller expansion Q Hong, B Fei, H Wu, MA Perkowski, N Zhuang [1993] Proceedings of the Twenty-Third International Symposium on Multiple …, 1993 | 17 | 1993 |
| Efficient computation for ternary Reed-Muller expansions under fixed polarities B Fei, Q Hong, H Wu, MA Perkowski, N Zhuang International Journal of Electronics Theoretical and Experimental 75 (4 …, 1993 | 16 | 1993 |
| PTM: Technology mapper for pass-transistor logic N Zhuang, MV Scotti, PYK Cheung IEE Proceedings-Computers and Digital Techniques 146 (1), 13-19, 1999 | 9 | 1999 |
| Logic synthesis for a fine-grain FPGA N Zhuang, PYK Cheung IEE Proceedings-Computers and Digital Techniques 145 (1), 47-51, 1998 | 8 | 1998 |
| Synthesis of Multiplexer Directed-Acyclic-Graph network with application to FPGAs and BDDs H Wu, M Perkowski, N Zhuang Proc. IWLS 93, 1993 | 6 | 1993 |
| Research into ternary edge-triggered JKL flip-flop W Haomin, Z Nan Journal of Electronics (China) 8 (3), 268-275, 1991 | 5 | 1991 |
| Calculation of ternary mixed polarity function vector B Fei, Q Hong, N Zhuang [1993] Proceedings of the Twenty-Third International Symposium on Multiple …, 1993 | 4 | 1993 |
| Fast logic synthesis based upon ternary universal logic module U/sub f B Fei, N Zhuang 1992 Proceedings The Twenty-Second International Symposium on Multiple …, 1992 | 4 | 1992 |
| Synthesis for Reed-Muller directed acyclic graph network H Wu, N Zhuang, MA Perkowski IEE Proceedings E (Computers and Digital Techniques) 140 (6), 357-360, 1993 | 2 | 1993 |
| Novel modulo-N counter H Wu, N Zhuang International journal of electronics 71 (5), 821-826, 1991 | 2 | 1991 |
| Using Genetic Algorithm in Binate Covering for LUT-based FPGA Technology Mapping N Zhuang, PYK Cheung URL: citeseer. nj. nec. com/50251. html, 0 | 2 | |
| Vector algorithm for Reed-Muller expansions TG Clarkson, N Zhuang Electronics Letters 30 (7), 549-550, 1994 | 1 | 1994 |
| Novel CMOS scan design for VLSI testability H Wu, N Zhuang, MA Perkowski [1993] Proceedings of the Twenty-Third International Symposium on Multiple …, 1993 | 1 | 1993 |