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Tuo-Hung (Alex) Hou
Tuo-Hung (Alex) Hou
Institute of Electronics; National Yang Ming Chiao Tung University
Email confirmado em nycu.edu.tw
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Recommended methods to study resistive switching devices
M Lanza, HSP Wong, E Pop, D Ielmini, D Strukov, BC Regan, L Larcher, ...
Advanced Electronic Materials 5 (1), 1800143, 2019
6632019
Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics
A Kerber, E Cartier, L Pantisano, R Degraeve, T Kauerauf, Y Kim, A Hou, ...
IEEE Electron Device Letters 24 (2), 87-89, 2003
4552003
Electrode dependence of filament formation in HfO2 resistive-switching memory
KL Lin, TH Hou, J Shieh, JH Lin, CT Chou, YJ Lee
Journal of Applied Physics 109 (8), 2011
3722011
Mitigating effects of non-ideal synaptic device characteristics for on-chip learning
PY Chen, B Lin, IT Wang, TH Hou, J Ye, S Vrudhula, J Seo, Y Cao, S Yu
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 194-199, 2015
2962015
Bipolar Nonlinear Selector for 1S1R Crossbar Array Applications
JJ Huang, YM Tseng, CW Hsu, TH Hou
IEEE Electron Device Letters 32 (10), 1427-1429, 2011
2282011
Optically initialized robust valley-polarized holes in monolayer WSe2
WT Hsu, YL Chen, CH Chen, PS Liu, TH Hou, LJ Li, WH Chang
Nature communications 6 (1), 8963, 2015
2192015
Transition of stable rectification to resistive-switching in Ti/TiO2/Pt oxide diode
JJ Huang, CW Kuo, WC Chang, TH Hou
Applied Physics Letters 96 (26), 2010
2122010
Characterization and Modeling of Nonfilamentary Ta/TaOx/TiO2/Ti Analog Synaptic Device
YF Wang, YC Lin, IT Wang, TP Lin, TH Hou
Scientific Reports 5 (1), 10150, 2015
2052015
3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications
IT Wang, CC Chang, LW Chiu, T Chou, TH Hou
Nanotechnology 27 (36), 365204, 2016
2022016
Standards for the characterization of endurance in resistive switching devices
M Lanza, R Waser, D Ielmini, JJ Yang, L Goux, J Suñe, AJ Kenyon, ...
ACS nano 15 (11), 17214-17231, 2021
1972021
Multi-level control of conductive nano-filament evolution in HfO 2 ReRAM by pulse-train operations
L Zhao, HY Chen, SC Wu, Z Jiang, S Yu, TH Hou, HSP Wong, Y Nishi
Nanoscale 6 (11), 5698-5702, 2014
1952014
Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application
CH Chen, TL Lee, TH Hou, CL Chen, CC Chen, JW Hsu, KL Cheng, ...
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 56-57, 2004
1822004
Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
L Gao, IT Wang, PY Chen, S Vrudhula, J Seo, Y Cao, TH Hou, S Yu
Nanotechnology 26 (45), 455204, 2015
1572015
One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications
JJ Huang, YM Tseng, WC Luo, CW Hsu, TH Hou
2011 international electron devices meeting, 31.7. 1-31.7. 4, 2011
1562011
Self-rectifying bipolar TaOx/TiO2 RRAM with superior endurance over 1012 cycles for 3D high-density storage-class memory
CW Hsu, IT Wang, CL Lo, MC Chiang, WY Jang, CH Lin, TH Hou
2013 Symposium on VLSI Technology, T166-T167, 2013
1522013
Mitigating asymmetric nonlinear weight update effects in hardware neural network based on analog resistive synapse
CC Chang, PC Chen, T Chou, IT Wang, B Hudec, CC Chang, CM Tsai, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (1 …, 2017
1332017
High-k gate stacks for planar, scaled CMOS integrated circuits
HR Huff, A Hou, C Lim, Y Kim, J Barnett, G Bersuker, GA Brown, ...
Microelectronic Engineering 69 (2-4), 152-167, 2003
1262003
3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation
IT Wang, YC Lin, YF Wang, CW Hsu, TH Hou
2014 IEEE international electron devices meeting, 28.5. 1-28.5. 4, 2014
1202014
Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication
HY Chen, S Brivio, CC Chang, J Frascaroli, TH Hou, B Hudec, M Liu, H Lv, ...
Journal of Electroceramics 39, 21-38, 2017
1142017
Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
TH Hou, MF Wang, CC Chen, CW Yang, LG Yao, SC Chen
US Patent 6,890,811, 2005
1092005
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