Josep Torrellas

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Jose RenauProcessor of Computer Science Engineering, UCSCE-mail confirmado em ucsc.edu
Luis CezeProfessor of Computer Science and Engineering, University of WashingtonE-mail confirmado em cs.washington.edu
Smruti R. SarangiComputer Science, IIT DelhiE-mail confirmado em cse.iitd.ac.in
Michael HuangUniversity of RochesterE-mail confirmado em rochester.edu
Radu TeodorescuThe Ohio State UniversityE-mail confirmado em cse.ohio-state.edu
Milos PrvulovicProfessor of Computer Science, Georgia TechE-mail confirmado em cc.gatech.edu
Pablo MontesinosAppleE-mail confirmado em apple.com
Wonsun AhnUniversity of PittsburghE-mail confirmado em cs.pitt.edu
José F. MartínezLee Teng-hui Professor of Engineering at Cornell UniversityE-mail confirmado em cornell.edu
Zheng ZhangProfessor of Computer Science and Engineering, NYU Shanghai; Director, Amazon Shanghai AI LabE-mail confirmado em nyu.edu
Lawrence RauchwergerProfessor of Computer Science, University of Illinois at Urbana-ChampaignE-mail confirmado em illinois.edu
Maria GarzaranResearch assistant professor, University of Illinois at Urbana-ChampaignE-mail confirmado em uiuc.edu
Ulya R. KarpuzcuElectrical and Computer Engineering, University of Minnesota, Twin-CitiesE-mail confirmado em umn.edu
Nam Sung KimW.J. ‘Jerry’ Sanders III – AMD, Inc. Endowed Chair Professor and Fellow of ACM/IEEEE-mail confirmado em illinois.edu
John HennessyStanford UniversityE-mail confirmado em stanford.edu
Aditya AgrawalSoftware Engineer, GoogleE-mail confirmado em illinois.edu
Calin CascavalGoogleE-mail confirmado em cascaval.us
David PaduaProfessor Emeritus, University of Illinois at Urbana-ChampaignE-mail confirmado em illinois.edu
Pedro TrancosoDepartment of Computer Science and Engineering, Chalmers University of TechnologyE-mail confirmado em chalmers.se
Abdullah MuzahidProfessor of Computer Science and Engineering, Texas A&M UniversityE-mail confirmado em tamu.edu

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Josep Torrellas

Professor of Computer Science, University of Illinois Urbana-Champaign

E-mail confirmado em illinois.edu - Página inicial

Computer architecture parallel computing shared-memory architectures


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VARIUS: A model of process variation and resulting timing errors for microarchitects SR Sarangi, B Greskamp, R Teodorescu, J Nakano, A Tiwari, J Torrellas IEEE Transactions on Semiconductor Manufacturing 21 (1), 3-13, 2008	532	2008
Variation-aware application scheduling and power management for chip multiprocessors R Teodorescu, J Torrellas ACM SIGARCH computer architecture news 36 (3), 363-374, 2008	447	2008
A chip-multiprocessor architecture with speculative multithreading V Krishnan, J Torrellas IEEE Transactions on Computers 48 (9), 866-880, 1999	443	1999
Bulk disambiguation of speculative threads in multiprocessors L Ceze, J Tuck, J Torrellas, C Cascaval ACM SIGARCH Computer Architecture News 34 (2), 227-238, 2006	429	2006
FlexRAM: Toward an advanced intelligent memory system Y Kang, W Huang, SM Yoo, D Keen, Z Ge, V Lam, P Pattnaik, J Torrellas 2012 IEEE 30th International Conference on Computer Design (ICCD), 5-14, 2012	392	2012
Invisispec: Making speculative execution invisible in the cache hierarchy M Yan, J Choi, D Skarlatos, A Morrison, C Fletcher, J Torrellas 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018	359	2018
ReVive: Cost-effective architectural support for rollback recovery in shared-memory multiprocessors M Prvulovic, Z Zhang, J Torrellas ACM SIGARCH Computer Architecture News 30 (2), 111-122, 2002	352	2002
False sharing and spatial locality in multiprocessor caches J Torrellas, HS Lam, JL Hennessy IEEE Transactions on Computers 43 (6), 651-663, 1994	342	1994
POSH: a TLS compiler that exploits program structure W Liu, J Tuck, L Ceze, W Ahn, K Strauss, J Renau, J Torrellas Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006	331	2006
BulkSC: Bulk enforcement of sequential consistency L Ceze, J Tuck, P Montesinos, J Torrellas Proceedings of the 34th annual international symposium on Computer …, 2007	319	2007
Facelift: Hiding and slowing down aging in multicores A Tiwari, J Torrellas 2008 41st IEEE/ACM International Symposium on Microarchitecture, 129-140, 2008	310	2008
Cache telepathy: Leveraging shared resource attacks to learn {DNN} architectures M Yan, CW Fletcher, J Torrellas 29th USENIX Security Symposium (USENIX Security 20), 2003-2020, 2020	302	2020
Delorean: Recording and deterministically replaying shared-memory multiprocessor execution ef? ciently P Montesinos, L Ceze, J Torrellas ACM SIGARCH Computer Architecture News 36 (3), 289-300, 2008	291	2008
Architectural support for scalable speculative parallelization in shared-memory multiprocessors M Cintra, JF Martínez, J Torrellas Proceedings of the 27th annual international symposium on Computer …, 2000	288	2000
Speculative synchronization: Applying thread-level speculation to explicitly parallel applications JF Martinez, J Torrellas ACM SIGOPS Operating Systems Review 36 (5), 18-29, 2002	273	2002
Cherry: Checkpointed early resource recycling in out-of-order microprocessors J Martínez, J Renau, M Huang, M Prvulovic, J Torrellas Intl. Symp. on Microarchitecture (MICRO), 2002	267	2002
Positional adaptation of processors: application to energy reduction MC Huang, J Renau, J Torrellas ACM SIGARCH Computer Architecture News 31 (2), 157-168, 2003	264	2003
Attack directories, not caches: Side channel attacks in a non-inclusive world M Yan, R Sprabery, B Gopireddy, C Fletcher, R Campbell, J Torrellas 2019 IEEE Symposium on Security and Privacy (SP), 888-904, 2019	246	2019
Speculative taint tracking (stt) a comprehensive protection for speculatively accessed data J Yu, M Yan, A Khyzha, A Morrison, J Torrellas, CW Fletcher Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019	235	2019
Using a user-level memory thread for correlation prefetching Y Solihin, J Lee, J Torrellas ACM SIGARCH Computer Architecture News 30 (2), 171-182, 2002	230	2002

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