| Resilient low voltage accelerators for high energy efficiency N Chandramoorthy, K Swaminathan, M Cochet, A Paidimarri, S Eldridge, ... 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 62 | 2019 |
| {PHMon}: A programmable hardware monitor and its security use cases L Delshadtehrani, S Canakci, B Zhou, S Eldridge, A Joshi, M Egele 29th USENIX Security Symposium (USENIX Security 20), 807-824, 2020 | 59 | 2020 |
| Neural network-based accelerators for transcendental function approximation S Eldridge, F Raudies, D Zou, A Joshi Proceedings of the 24th edition of the great lakes symposium on VLSI, 169-174, 2014 | 45 | 2014 |
| MLIR as hardware compiler infrastructure S Eldridge, P Barua, A Chapyzhenka, A Izraelevitz, J Koenig, C Lattner, ... Workshop on Open-Source EDA Technology (WOSET) 3, 2021 | 32 | 2021 |
| Towards General-Purpose Neural Network Computing S Eldridge, J Appavoo, A Joshi, A Waterland, M Seltzer Proceedings of the 2015 International Conference on Parallel Architecture …, 2015 | 30 | 2015 |
| Dyhard-dnn: Even more dnn acceleration with dynamic hardware reconfiguration M Putic, S Venkataramani, S Eldridge, A Buyuktosunoglu, P Bose, M Stan Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 28 | 2018 |
| Nile: A Programmable Monitoring Coprocessor L Delshadtehrani, S Eldridge, S Canakci, M Egele, A Joshi IEEE Computer Architecture Letters, 2017 | 25 | 2017 |
| Learning to navigate in a virtual world using optic flow and stereo disparity signals F Raudies, S Eldridge, A Joshi, M Versace Artificial Life and Robotics 19, 157-169, 2014 | 15 | 2014 |
| Self-evaluating array of memory A Buyuktosunoglu, S Venkataramani, R Joshi, KV Swaminathan, ... US Patent 10,607,715, 2020 | 12 | 2020 |
| Digest generation V Gopal, JD Guilford, S Eldridge, GM Wolrich, E Ozturk, WK Feghali US Patent 9,292,548, 2016 | 12 | 2016 |
| Very low voltage (VLV) design R Bertran, P Bose, D Brooks, J Burns, A Buyuktosunoglu, ... 2017 IEEE International Conference on Computer Design (ICCD), 601-604, 2017 | 11 | 2017 |
| Determination and correction of physical circuit event related errors of a hardware design P Bose, A Buyuktosunoglu, S Eldridge, KV Swaminathan, Y Zu US Patent 10,365,327, 2019 | 10 | 2019 |
| Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems S Eldridge, A Buyuktosunoglu, P Bose Second Workshop on Computer Architecture Research with RISC-V, 2018 | 10 | 2018 |
| Exploiting hidden layer modular redundancy for fault-tolerance in neural network accelerators S Eldridge, A Joshi Proc. Boston area ARChitecture (BARC) Workshop, 2015 | 6 | 2015 |
| A Low Voltage RISC-V Heterogeneous System S Eldridge, K Swaminathan, N Chandramoorthy, A Buyuktosunoglu, ... First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017 | 4 | 2017 |
| Low-overhead error prediction and preemption in deep neural network using apriori network statistics S Venkataramani, S Eldridge, KV Swaminathan, A Buyuktosunoglu, ... US Patent 11,016,840, 2021 | 3 | 2021 |
| MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA S Eldridge, R Bertran, A Buyuktosunoglu, P Bose 7th RISC-V Workshop, 2017 | 2 | 2017 |
| Neural Network Computing Using On-Chip Accelerators S Eldridge Boston University, 2016 | 2 | 2016 |
| Reducing the cost of n modular redundancy for neural networks P Bose, A Buyuktosunoglu, S Eldridge, KV Swaminathan, A Vega, ... US Patent 11,599,795, 2023 | 1 | 2023 |
| A Programmable Hardware Monitor for Security of RISC-V Processors L Delshadtehrani, S Canakci, B Zhou, S Eldridge, A Joshi, M Egele Boston Area Architecture Workshop (BARC), 2020 | 1 | 2020 |