| Wireless NoC as interconnection backbone for multicore chips: Promises and challenges S Deb, A Ganguly, PP Pande, B Belzer, D Heo IEEE Journal on emerging and selected topics in circuits and systems 2 (2 …, 2012 | 396 | 2012 |
| Scalable hybrid wireless network-on-chip architectures for multicore systems A Ganguly, K Chang, S Deb, PP Pande, B Belzer, C Teuscher IEEE Transactions on Computers 60 (10), 1485-1502, 2010 | 387 | 2010 |
| Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects S Deb, K Chang, X Yu, SP Sah, M Cosic, A Ganguly, PP Pande, B Belzer, ... IEEE Transactions on Computers 62 (12), 2382-2396, 2012 | 247 | 2012 |
| Performance evaluation and design trade-offs for wireless network-on-chip architectures K Chang, S Deb, A Ganguly, X Yu, SP Sah, PP Pande, B Belzer, D Heo ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (3), 1-25, 2012 | 157 | 2012 |
| Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects A Ganguly, PP Pande, B Belzer IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (11 …, 2009 | 140 | 2009 |
| Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects S Deb, A Ganguly, K Chang, P Pande, B Beizer, D Heo ASAP 2010-21st IEEE International Conference on Application-specific Systems …, 2010 | 126 | 2010 |
| A wireless interconnection framework for seamless inter and intra-chip communication in multichip systems MS Shamim, N Mansoor, RS Narde, V Kothandapani, A Ganguly, ... IEEE Transactions on Computers 66 (3), 389-402, 2016 | 104 | 2016 |
| Design of low power & reliable networks on chip through joint crosstalk avoidance and forward error correction coding PP Pande, A Ganguly, B Feero, B Belzer, C Grecu 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2006 | 81 | 2006 |
| CDMA enabled wireless network-on-chip V Vijayakumaran, MP Yuvaraj, N Mansoor, N Nerurkar, A Ganguly, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 10 (4), 1-20, 2014 | 74 | 2014 |
| A review of in-memory computing architectures for machine learning applications S Bavikadi, PR Sutradhar, KN Khasawneh, A Ganguly, ... Proceedings of the 2020 on Great Lakes Symposium on VLSI, 89-94, 2020 | 73 | 2020 |
| Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding A Ganguly, PP Pande, B Belzer, C Grecu Journal of electronic testing 24, 67-81, 2008 | 67 | 2008 |
| Design space exploration for wireless NoCs incorporating irregular network routing P Wettin, R Kim, J Murray, X Yu, PP Pande, A Ganguly, D Heoamlan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 61 | 2014 |
| Hybrid wireless network on chip: A new paradigm in multi-core design PP Pande, A Ganguly, K Chang, C Teuscher Proceedings of the 2nd international Workshop on Network on Chip …, 2009 | 60 | 2009 |
| Complex network inspired fault-tolerant NoC architectures with wireless links A Ganguly, P Wettin, K Chang, P Pande Proceedings of the fifth ACM/IEEE International Symposium on Networks-on …, 2011 | 57 | 2011 |
| Design of an efficient NoC architecture using millimeter-wave wireless links S Deb, K Chang, A Ganguly, X Yu, C Teuscher, P Pande, D Heo, B Belzer Thirteenth International Symposium on Quality Electronic Design (ISQED), 165-172, 2012 | 53 | 2012 |
| Reconfigurable wireless network-on-chip with a dynamic medium access mechanism N Mansoor, A Ganguly Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015 | 52 | 2015 |
| Interference-aware wireless network-on-chip architecture using directional antennas HK Mondal, SH Gade, MS Shamim, S Deb, A Ganguly IEEE Transactions on Multi-Scale Computing Systems 3 (3), 193-205, 2016 | 51 | 2016 |
| Energy reduction through crosstalk avoidance coding in NoC paradigm PP Pande, H Zhu, A Ganguly, C Grecu 9th EUROMICRO Conference on Digital System Design (DSD'06), 689-695, 2006 | 47 | 2006 |
| A survey on machine learning accelerators and evolutionary hardware platforms S Bavikadi, A Dhavlle, A Ganguly, A Haridass, H Hendy, C Merkel, ... IEEE Design & Test 39 (3), 91-116, 2022 | 46 | 2022 |
| pPIM: A programmable processor-in-memory architecture with precision-scaling for deep learning PR Sutradhar, M Connolly, S Bavikadi, SMP Dinakarrao, MA Indovina, ... IEEE Computer Architecture Letters 19 (2), 118-121, 2020 | 44 | 2020 |
Partha PandeWashington State UniversityE-mail confirmado em wsu.edu
