| ASAP7: A 7-nm finFET predictive process design kit LT Clark, V Vashishtha, L Shifren, A Gujja, S Sinha, B Cline, ... Microelectronics Journal 53, 105-115, 2016 | 577 | 2016 |
| Exploring sub-20nm FinFET design with predictive technology models S Sinha, G Yeric, V Chandra, B Cline, Y Cao Proceedings of the 49th Annual Design Automation Conference, 283-288, 2012 | 382 | 2012 |
| Physically-based models for effective mobility and local-field mobility of electrons in MOS inversion layers H Shin, GM Yeric, AF Tasch, CM Maziar Solid-State Electronics 34 (6), 545-552, 1991 | 127 | 1991 |
| Correlated electron switch programmable fabric L Shifren, G Yeric, S Sinha, B Cline, V Chandra US Patent 10,056,143, 2018 | 93 | 2018 |
| Self-aligned double patterning aware pin access and standard cell layout co-optimization X Xu, B Cline, G Yeric, B Yu, DZ Pan Proceedings of the 2014 on International symposium on physical design, 101-108, 2014 | 89 | 2014 |
| Device and technology implications of the Internet of Things R Aitken, V Chandra, J Myers, B Sandhu, L Shifren, G Yeric 2014 symposium on VLSI technology (VLSI-technology): digest of technical …, 2014 | 86 | 2014 |
| Moore's law at 50: Are we planning for retirement? G Yeric 2015 IEEE International Electron Devices Meeting (IEDM), 1.1. 1-1.1. 8, 2015 | 84 | 2015 |
| Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools K Chang, S Sinha, B Cline, R Southerland, M Doherty, G Yeric, SK Lim 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 68 | 2016 |
| Standard cell library design and optimization methodology for ASAP7 PDK X Xu, N Shah, A Evans, S Sinha, B Cline, G Yeric 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 999 …, 2017 | 54 | 2017 |
| Replacing copper interconnects with graphene at a 7-nm node NC Wang, S Sinha, B Cline, CD English, G Yeric, E Pop 2017 IEEE International Interconnect Technology Conference (IITC), 1-3, 2017 | 46 | 2017 |
| 32-bit processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance CS Lee, B Cline, S Sinha, G Yeric, HSP Wong 2016 IEEE international electron devices meeting (IEDM), 28.3. 1-28.3. 4, 2016 | 40 | 2016 |
| Design benchmarking to 7nm with FinFET predictive technology models S Sinha, B Cline, G Yeric, V Chandra, Y Cao Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 40 | 2012 |
| Physical design and FinFETs R Aitken, G Yeric, B Cline, S Sinha, L Shifren, I Iqbal, V Chandra Proceedings of the 2014 on International symposium on physical design, 65-68, 2014 | 37 | 2014 |
| A universal MOSFET mobility degradation model for circuit simulation GM Yeric, AF Tasch, SK Banerjee IEEE transactions on computer-aided design of integrated circuits and …, 1990 | 36 | 1990 |
| The past present and future of design-technology co-optimization G Yeric, B Cline, S Sinha, D Pietromonaco, V Chandra, R Aitken Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-8, 2013 | 35 | 2013 |
| Predictive simulation and benchmarking of Si and Ge pMOS FinFETs for future CMOS technology L Shifren, R Aitken, AR Brown, V Chandra, B Cheng, C Riddet, ... IEEE Transactions on Electron Devices 61 (7), 2271-2277, 2014 | 32 | 2014 |
| Asymmetric correlated electron switch operation L Shifren, G Yeric US Patent 9,755,146, 2017 | 28 | 2017 |
| Power benefit study of monolithic 3D IC at the 7nm technology node K Chang, K Acharya, S Sinha, B Cline, G Yeric, SK Lim 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 28 | 2015 |
| Simulation study of the impact of quantum confinement on the electrostatically driven performance of n-type nanowire transistors Y Wang, T Al-Ameri, X Wang, VP Georgiev, E Towie, SM Amoroso, ... IEEE Transactions on Electron Devices 62 (10), 3229-3236, 2015 | 26 | 2015 |
| A 65-nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software M Karthikeyan, S Fox, W Cote, G Yeric, M Hall, J Garcia, B Mitchell, E Wolf, ... IEEE transactions on semiconductor manufacturing 21 (2), 161-168, 2008 | 25 | 2008 |