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Gabriel Wicaksana Satryajie
Gabriel Wicaksana Satryajie
E-mail confirmado em students.undip.ac.id
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Improvement of FinFET electrical characteristics by hydrogen annealing
W Xiong, G Gebara, J Zaman, M Gostkowski, B Nguyen, G Smith, D Lewis, ...
IEEE Electron Device Letters 25 (8), 541-543, 2004
1862004
Conventional n-channel MOSFET devices using single layer HfO/sub 2/and ZrO/sub 2/as high-k gate dielectrics with polysilicon gate electrode
Y Kim, G Gebara, M Freiler, J Barnett, D Riley, J Chen, K Torres, JE Lim, ...
International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001
932001
Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility
W Xiong, CR Cleavelin, P Kohli, C Huffman, T Schulz, K Schruefer, ...
IEEE Electron Device Letters 27 (7), 612-614, 2006
832006
Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap
X Sun, Q Lu, V Moroz, H Takeuchi, G Gebara, J Wetzel, S Ikeda, C Shin, ...
IEEE Electron Device Letters 29 (5), 491-493, 2008
822008
Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme
HR Harris, P Kalra, P Majhi, M Hussain, D Kelly, J Oh, D He, C Smith, ...
2007 IEEE Symposium on VLSI Technology, 154-155, 2007
722007
Body effect in tri-and pi-gate SOI MOSFETs
J Frei, C Johns, A Vazquez, W Xiong, CR Cleavelin, T Schulz, ...
IEEE electron device letters 25 (12), 813-815, 2004
702004
Methods for nanoscale feature imprint molding
MM Hussain, N Moumen, G Gebara, E Labelle, S Lanee, B Sassman, ...
US Patent 7,736,954, 2010
582010
IEDM Tech. Digest
Y Kim, G Gebara, M Freiler
Digest, 2001
382001
Integration of high-k gate stack systems into planar CMOS process flows
HR Huff, A Agarwal, Y Kim, L Perrymore, D Riley, J Barnett, C Sparks, ...
Extended Abstracts of International Workshop on Gate Insulator. IWGI 2001 …, 2001
212001
Fin thickness asymmetry effects in multiple-gate SOI FETs (MuGFETs)
T Schulz, W Xiong, CR Cleavelin, K Schruefer, M Gostkowski, K Matthews, ...
2005 IEEE International SOI Conference Proceedings, 154-156, 2005
192005
Plasma-Induced Damage in High-/Metal Gate Stack Dry Etch
MM Hussain, SC Song, J Barnett, CY Kang, G Gebara, B Sassman, ...
IEEE electron device letters 27 (12), 972-974, 2006
172006
Silicon superlattice on SOI for high mobility and reduced leakage
RJ Mears, M Hytha, I Dukovski, A Yiptong, X Huang, S Halilov, A Broka, ...
2007 IEEE International SOI Conference, 23-24, 2007
122007
Deposition thickness based high-throughput nano-imprint template
MM Hussain, E Labelle, B Sassman, G Gebara, S Lanee, N Moumen, ...
Microelectronic engineering 84 (4), 594-598, 2007
92007
Conventional n-channel MOSFET devices using single layer and as high- gate dielectrics with polysilicon gate electrode
Y Kim, G Gebara, M Freiler, J Barnett, D Riley
IEDM Tech. Dig., 455-458, 2001
92001
Dual work function high-k/metal gate CMOS FinFETs
MM Hussain, C Smith, P Kalra, JW Yang, G Gebara, B Sassman, P Kirsch, ...
ESSDERC 2007-37th European Solid State Device Research Conference, 207-209, 2007
82007
Experimental Observations of the Redistribution of Implanted Nitrogen at the Si-SiO2 Interface During RTA Processing
PS Lysaght, B Nguyen, J Bennett, G Williamson, K Torres, M Gilmer, ...
MRS Online Proceedings Library (OPL) 568, 283, 1999
31999
Highly selective isotropic dry etch based nanofabrication
MM Hussain, G Gebara, B Sassman, S Lanee, L Larson
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2007
22007
Systems and methods for detecting watermark formations on semiconductor wafers
K Mori, S Ikeda, G Gebara
US Patent 8,580,696, 2013
2013
BACKEND DEVELOPMENT FOR 0.59 MICRON BURIED CHANNEL CMOS
WG Waldo, R Turkman, K Schwechel, G Gebara, J Toler, L Hernandez
Proceedings, 271, 1996
1996
Novel Dual Bit Tri-Gate Charge-Trapping Memory Devices.................................................... M. Specht, R. Kömmling, F. Hofmann, V. Klandzievski, L. Dreeskornfeld …
TS Cleavelin, N Chaudhary, G Gebara, JR Zaman, M Gostkowski, ...
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