| Dynamic binary translation and optimization K Ebcioglu, E Altman, M Gschwind, S Sathaye IEEE Transactions on computers 50 (6), 529-548, 2001 | 234 | 2001 |
| Dynamic and transparent binary translation M Gschwind, ER Altman, S Sathaye, P Ledak, D Appenzeller Computer 33 (3), 54-59, 2000 | 193 | 2000 |
| Methods and apparatus for reordering and renaming memory references in a multiprocessor computer system E Altman, K Ebcioglu, M Gschwind, S Sathaye US Patent 6,349,361, 2002 | 190 | 2002 |
| Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ... US Patent 6,779,049, 2004 | 111 | 2004 |
| Advances and future challenges in binary translation and optimization ER Altman, K Ebcioglu, M Gschwind, S Sathaye Proceedings of the IEEE 89 (11), 1710-1722, 2001 | 108 | 2001 |
| Instruction fetch mechanisms for VLIW architectures with compressed encodings TM Conte, S Banerjia, SY Larin, KN Menezes, SW Sathaye Proceedings of the 29th Annual IEEE/ACM International Symposium on …, 1996 | 105 | 1996 |
| Method and apparatus for implementing execution predicates in a computer processing system MK Gschwind, S Sathaye US Patent 6,513,109, 2003 | 95 | 2003 |
| Method and system for multiprocessor emulation on a multiprocessor host system ER Altman, R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener, ... US Patent 7,496,494, 2009 | 82 | 2009 |
| BOA: The architecture of a binary translation processor E Altman, M Gschwind, S Sathaye, S Kosonocky, A Bright, J Fritts, ... IBM Research Report RC 21665, 2000 | 78 | 2000 |
| Dynamic rescheduling: A technique for object code compatibility in VLIW architectures TM Conte, SW Sathaye Proceedings of the 28th Annual International Symposium on Microarchitecture …, 1995 | 72 | 1995 |
| Optimizations and oracle parallelism with dynamic translation K Ebcioglu, ER Altman, S Sathaye, M Gschwind MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999 | 64 | 1999 |
| BOA: Targeting multi-gigahertz with binary translation S Sathaye, P Ledak, J Leblanc, S Kosonocky, M Gschwind, J Fritts, Z Filan, ... Proc. of the 1999 Workshop on Binary Translation, 2-11, 1999 | 62 | 1999 |
| Structure for instruction cache trace formation GT Davis, RW Doing, JD Jabusch, MVVA Krishna, B Olsson, EF Robinson, ... US Patent App. 12/131,442, 2008 | 58 | 2008 |
| Binary translation and architecture convergence issues for IBM System/390 M Gschwind, K Ebcioğlu, E Altman, S Sathaye Proceedings of the 14th international conference on Supercomputing, 336-347, 2000 | 55 | 2000 |
| Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ... US Patent 6,907,477, 2005 | 53 | 2005 |
| Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture E Altman, M Gschwind, D Prener, J Rivers, S Sathaye, JD Wellman, ... US Patent App. 11/047,983, 2006 | 47 | 2006 |
| Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host ER Altman, R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener, ... US Patent 7,953,588, 2011 | 45 | 2011 |
| Execution-based scheduling for VLIW architectures K Ebcioğlu, ER Altman, S Sathaye, M Gschwind European Conference on Parallel Processing, 1269-1280, 1999 | 45 | 1999 |
| System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design TM Conte, KN Menezes, SW Sathaye, MC Toburen IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (2), 129-137, 2000 | 44 | 2000 |
| System and method of execution of register pointer instructions ahead of instruction issues E Altman, MK Gschwind, JA Rivers, SW Sathaye, JD Wellman, V Zyuban US Patent 7,496,733, 2009 | 37 | 2009 |
