| Utilizing atomic layer deposition for programmable device TA Lowrey, CH Dennison US Patent 6,511,867, 2003 | 458 | 2003 |
| Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base … C Dennison US Patent 6,534,781, 2003 | 448 | 2003 |
| Method for forming phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and … C Dennison US Patent 6,593,176, 2003 | 447 | 2003 |
| Reduced area intersection between electrode and programming element CH Dennison, GC Wicker, TA Lowrey, SJ Hudgens, C Chiang, D Xu US Patent 6,673,700, 2004 | 428 | 2004 |
| Reduced area intersection between electrode and programming element CH Dennison, AT Wang, PK Chaturbhai, JC Chow US Patent 6,605,527, 2003 | 420 | 2003 |
| Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography TA Lowrey, RW Chance, DM Durcan, R Lee, CH Dennison, YC Liu, ... US Patent 5,013,680, 1991 | 339 | 1991 |
| Phase change memory BG Johnson, CH Dennison US Patent 6,791,102, 2004 | 325 | 2004 |
| Phase change memory device on a planar composite layer CH Dennison US Patent 6,744,088, 2004 | 289 | 2004 |
| Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts CH Dennison US Patent 5,292,677, 1994 | 261 | 1994 |
| Method of forming a bit line over capacitor array of memory cells CH Dennison, A Ahmad US Patent 5,338,700, 1994 | 254 | 1994 |
| Silicon on insulator DRAM process utilizing both fully and partially depleted devices CH Dennison, JK Zahurak US Patent 6,818,496, 2004 | 248 | 2004 |
| Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory C Dennison US Patent 6,696,355, 2004 | 234 | 2004 |
| Lower electrode isolation in a double-wide trench C Dennison US Patent 6,646,297, 2003 | 226 | 2003 |
| Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon CH Dennison, RPS Thakur US Patent 5,340,765, 1994 | 216 | 1994 |
| Semiconductor processing methods of forming stacked capacitors CH Dennison, MA Walker US Patent 5,498,562, 1996 | 208 | 1996 |
| Method of forming a bit line over capacitor array of memory cells CH Dennison US Patent 5,401,681, 1995 | 198 | 1995 |
| Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer CH Dennison US Patent 5,330,879, 1994 | 193 | 1994 |
| Multi-pin stacked capacitor utilizing micro villus patterning in a container cell and method to fabricate same CH Dennison US Patent 5,340,763, 1994 | 192 | 1994 |
| Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby C Dennison US Patent 6,649,928, 2003 | 190 | 2003 |
| Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing CH Dennison, MA Walker US Patent 5,270,241, 1993 | 184 | 1993 |
