| Adaptive placement and migration policy for an STT-RAM-based hybrid cache Z Wang, DA Jiménez, C Xu, G Sun, Y Xie 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 173 | 2014 |
| Perceptron learning for reuse prediction E Teran, Z Wang, DA Jiménez 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 159 | 2016 |
| Detecting and mitigating data-dependent DRAM failures by exploiting current memory content S Khan, C Wilkerson, Z Wang, AR Alameldeen, D Lee, O Mutlu Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 118 | 2017 |
| Aggregated write back in a direct mapped two level memory Z Wang, CB Wilkerson, ZA Chishti US Patent 10,496,544, 2019 | 75 | 2019 |
| WADE: Writeback-aware dynamic cache management for NVM-based main memory system Z Wang, S Shan, T Cao, J Gu, Y Xu, S Mu, Y Xie, DA Jiménez ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-21, 2013 | 59 | 2013 |
| Improving writeback efficiency with decoupled last-write prediction Z Wang, SM Khan, DA Jiménez ACM SIGARCH Computer Architecture News 40 (3), 309-320, 2012 | 46 | 2012 |
| Decoupled dynamic cache segmentation SM Khan, Z Wang, DA Jiménez IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 34 | 2012 |
| Minimal disturbance placement and promotion E Teran, Y Tian, Z Wang, DA Jiménez 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 18 | 2016 |
| Building a low latency, highly associative dram cache with the buffered way predictor Z Wang, DA Jiménez, T Zhang, GH Loh, Y Xie 2016 28th International Symposium on Computer Architecture and High …, 2016 | 12 | 2016 |
| Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory Z Wang, CB Wilkerson, ZA Chishti, SH Pugsley, AR Alameldeen, SLL Lu US Patent 10,261,901, 2019 | 11 | 2019 |
| Multi-level system memory with near memory scrubbing based on predicted far memory idle time Z Wang, CB Wilkerson, ZA Chishti US Patent 10,120,806, 2018 | 10 | 2018 |
| 23.9 An 8-channel 4.5 Gb 180GB/s 18ns-row-latency RAM for the last level cache TKJ Ting, GB Wang, MH Wang, CP Wu, CK Wang, CW Lo, LC Tien, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 404-405, 2017 | 9 | 2017 |
| Method and apparatus related to cache memory Z Wang, J Gu, Y Xu US Patent 9,552,301, 2017 | 8 | 2017 |
| Multi-level memory management CB Wilkerson, AR Alameldeen, Z Wang, ZA Chishti US Patent 9,583,182, 2017 | 7 | 2017 |
| Rank idle time prediction driven last-level cache writeback Z Wang, SM Khan, DA Jiménez Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance …, 2012 | 7 | 2012 |
| Cache architecture using way ID to reduce near memory traffic in a two-level memory system Z Wang, AR Alameldeen US Patent 10,884,927, 2021 | 6 | 2021 |
| Multi-level memory management CB Wilkerson, AR Alameldeen, Z Wang, ZA Chishti US Patent 9,921,961, 2018 | 6 | 2018 |
| Studying microarchitectural structures with object code reordering SMF Rahman, Z Wang, DA Jiménez Proceedings of the Workshop on Binary Instrumentation and Applications, 7-16, 2009 | 6 | 2009 |
| 一种基于立体视觉的运动目标检测算法 王哲， 常发亮 计算机应用 26 (11), 2724-2726, 2006 | 6 | 2006 |
| Multi-level system memory with a battery backed up portion of a non volatile memory level Z Wang, AR Alameldeen US Patent App. 16/262,691, 2019 | 4 | 2019 |
Daniel A. JiménezDepartment of Computer Science and Engineering, Texas A&M UniversityE-mail confirmado em acm.org
