Jose Flich

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Olav LysneProfessor, Simula Research LaboratoryZweryfikowany adres z simula.no
Carles HernándezUniversitat Politècnica de ValènciaZweryfikowany adres z upv.es
Federico SillaFull Professor at Universitat Politecnica de Valencia, SpainZweryfikowany adres z disca.upv.es
Samuel Rodrigo MocholíNumascale ASZweryfikowany adres z pm.me
Manuel Perez MalumbresProfessor of Computer Engineering, Miguel Hernandez UniversityZweryfikowany adres z umh.es
Jesus Escudero-SahuquilloUniversity of Castilla-La ManchaZweryfikowany adres z uclm.es
Sven-Arne ReinemoResearch Director, Senior Research Scientist, Simula Metropolitan Centre for Digital EngineeringZweryfikowany adres z simula.no
Tomas RokickiZweryfikowany adres z cs.stanford.edu
Michihiro KoibuchiNational Institute of Informatics, JAPANZweryfikowany adres z nii.ac.jp
Ernst Gunnar GranAssociate Professor, NTNU; Senior Research Scientist, Simula Research LaboratoryZweryfikowany adres z simula.no
Manuel E. AcacioProfessor of Computer Science (Universidad de Murcia - SPAIN)Zweryfikowany adres z ditec.um.es
Julio SahuquilloProfessor, Universitat Politecnica de Valencia, SpainZweryfikowany adres z disca.upv.es
Alejandro MartínezARM Ltd.Zweryfikowany adres z arm.com
Gaspar MoraArchitect, NvidiaZweryfikowany adres z nvidia.com
Pasi LiljebergProfessor in Health Technology, University of Turku, FinlandZweryfikowany adres z utu.fi
Masoumeh (Azin) EbrahimiAssociate professor at KTH, SwedenZweryfikowany adres z kth.se
Juha PlosilaProfessor, University of Turku (UTU), FinlandZweryfikowany adres z utu.fi
Masoud DaneshtalabProfessor, Mälardalen University (Sweden), TalTech (Estonia)Zweryfikowany adres z mdh.se
Frank Olaf Sem-jacobsenSystem Engineer, Statsat ASZweryfikowany adres z ifi.uio.no
Maurizio PalesiAssociate Professor, University of Catania, ItalyZweryfikowany adres z dieei.unict.it

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Jose Flich

Associate Professor, Technical University of Valencia

Zweryfikowany adres z disca.upv.es

Computer Architecture on-chip communication


Tytuł Sortuj wg cytatów Sortuj wg roku Sortuj wg tytułu	Cytowane przez Cytowane przez	Rok
Segment-based routing: An efficient fault-tolerant routing algorithm for meshes and tori A Mejia, J Flich, J Duato, SA Reinemo, T Skeie Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006	170	2006
A new scalable and cost-effective congestion management strategy for lossless multistage interconnection networks J Duato, I Johnson, J Flich, F Naven, P Garcia, T Nachiondo 11th International Symposium on High-Performance Computer Architecture, 108-119, 2005	168	2005
A survey and evaluation of topology-agnostic deterministic routing algorithms J Flich, T Skeie, A Mejia, O Lysne, P Lopez, A Robles, J Duato, ... IEEE Transactions on Parallel and Distributed Systems 23 (3), 405-425, 2011	132	2011
Efficient unicast and multicast support for CMPs S Rodrigo, J Flich, J Duato, M Hummel 2008 41st IEEE/ACM International Symposium on Microarchitecture, 364-375, 2008	121	2008
Designing network on-chip architectures in the nanoscale era J Flich, D Bertozzi CRC press, 2010	120	2010
A routing methodology for achieving fault tolerance in direct networks ME Gomez, NA Nordbotten, J Flich, P Lopez, A Robles, J Duato, T Skeie, ... IEEE transactions on Computers 55 (4), 400-415, 2006	120	2006
Logic-based distributed routing for NoCs J Flich, J Duato IEEE computer architecture letters 7 (1), 13-16, 2008	118	2008
Addressing manufacturing challenges with cost-efficient fault tolerant routing S Rodrigo, J Flich, A Roca, S Medardoni, D Bertozzi, J Camacho, F Silla, ... 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 25-32, 2010	116	2010
Path-based partitioning methods for 3D networks-on-chip with minimal adaptive routing M Ebrahimi, M Daneshtalab, P Liljeberg, J Plosila, J Flich, H Tenhunen IEEE Transactions on Computers 63 (3), 718-733, 2012	106	2012
Region-based routing: An efficient routing mechanism to tackle unreliable hardware in network on chips J Flich, A Mejia, P Lopez, J Duato First International Symposium on Networks-on-Chip (NOCS'07), 183-194, 2007	100	2007
Region-based routing: a mechanism to support efficient routing algorithms in NoCs A Mejia, M Palesi, J Flich, S Kumar, P López, R Holsmark, J Duato IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (3), 356-369, 2009	99	2009
An efficient implementation of distributed routing algorithms for NoCs J Flich, S Rodrigo, J Duato Second ACM/ieee international symposium on networks-on-chip (NOCs 2008), 87-96, 2008	93	2008
Method for congestion management of a network, a signalling protocol, a switch, an end station and a network F Naven, ID Johnson, J Duato, J Flich US Patent 8,174,978, 2012	77	2012
An efficient and deadlock-free network reconfiguration protocol O Lysne, JM Montanana, J Flich, J Duato, TM Pinkston, T Skeie IEEE Transactions on Computers 57 (6), 762-779, 2008	72	2008
An efficient fault-tolerant routing methodology for meshes and tori ME Gomez, J Duato, J Flich, P Lopez, A Robles, NA Nordbotten, O Lysne, ... IEEE Computer Architecture Letters 3 (1), 3-3, 2004	72	2004
Efficient implementation of distributed routing algorithms for NoCs S Rodrigo, S Medardoni, J Flich, D Bertozzi, J Duato IET computers & digital techniques 3 (5), 460-475, 2009	70	2009
Efficient, scalable congestion management for interconnection networks PJ García, FJ Quiles, J Flich, J Duato, I Johnson, F Naven IEEE Micro 26 (5), 52-66, 2006	70	2006
Dynamic evolution of congestion trees: Analysis and impact on switch architecture PJ García, J Flich, J Duato, I Johnson, FJ Quiles, F Naven International Conference on High-Performance Embedded Architectures and …, 2005	67	2005
LASH-TOR: A generic transition-oriented routing algorithm T Skeie, O Lysne, J Flich, P Lopez, A Robles, J Duato Proceedings. Tenth International Conference on Parallel and Distributed …, 2004	67	2004
Improving routing performance in Myrinet networks J Flich, MP Malumbres, P Lopez, J Duato Proceedings 14th International Parallel and Distributed Processing Symposium …, 2000	63	2000

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