| Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ... IEEE transactions on very large scale integration (VLSI) systems 25 (10 …, 2017 | 537 | 2017 |
| Design issues and considerations for low-cost 3-D TSV IC technology G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ... IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010 | 400 | 2010 |
| Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ... 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 290 | 2017 |
| GAP-8: A RISC-V SoC for AI at the Edge of the IoT E Flamand, D Rossi, F Conti, I Loi, A Pullini, F Rotenberg, L Benini 2018 IEEE 29th International Conference on Application-specific Systems …, 2018 | 251 | 2018 |
| Network-on-chip design and synthesis outlook D Atienza, F Angiolini, S Murali, A Pullini, L Benini, G De Micheli Integration 41 (3), 340-359, 2008 | 213 | 2008 |
| Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing A Pullini, D Rossi, I Loi, G Tagliavini, L Benini IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019 | 176 | 2019 |
| An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ... IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017 | 161 | 2017 |
| PULP: A parallel ultra low power platform for next generation IoT applications D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015 | 158 | 2015 |
| Fault tolerance overhead in network-on-chip flow control schemes A Pullini, F Angiolini, D Bertozzi, L Benini Proceedings of the 18th annual symposium on Integrated circuits and system …, 2005 | 137 | 2005 |
| PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision F Conti, D Rossi, A Pullini, I Loi, L Benini Journal of Signal Processing Systems 84, 339-354, 2016 | 117 | 2016 |
| PULPino: A small single-core RISC-V SoC A Traber, F Zaruba, S Stucki, A Pullini, G Haugou, E Flamand, ... 3rd RISCV Workshop, 15, 2016 | 103 | 2016 |
| Quentin: an ultra-low-power pulpissimo soc in 22nm fdx PD Schiavone, D Rossi, A Pullini, A Di Mauro, F Conti, L Benini 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 102 | 2018 |
| Bringing NoCs to 65 nm A Pullini, F Angiolini, S Murali, D Atienza, G De Micheli, L Benini IEEE Micro 27 (5), 75-85, 2007 | 101 | 2007 |
| Vega: A ten-core SoC for IoT endnodes with DNN acceleration and cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ... IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021 | 98 | 2021 |
| Networks on chips: From research to products G De Micheli, C Seiculescu, S Murali, L Benini, F Angiolini, A Pullini Proceedings of the 47th Design Automation Conference, 300-305, 2010 | 98 | 2010 |
| NoC design and implementation in 65nm technology A Pullini, F Angiolini, P Meloni, D Atienza, S Murali, L Raffo, G De Micheli, ... First International Symposium on Networks-on-Chip (NOCS'07), 273-282, 2007 | 80 | 2007 |
| A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ... Solid-State Electronics 117, 170-184, 2016 | 79 | 2016 |
| Mr. wolf: A 1 gflop/s energy-proportional parallel ultra low power soc for iot edge processing A Pullini, D Rossi, I Loi, A Di Mauro, L Benini ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 76 | 2018 |
| Energy-efficient near-threshold parallel computing: The PULPv2 cluster D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ... Ieee Micro 37 (5), 20-31, 2017 | 75 | 2017 |
| 4.4 a 1.3 TOPS/W@ 32GOPS fully integrated 10-core SoC for IoT end-nodes with 1.7 μW cognitive wake-up from MRAM-based state-retentive sleep mode D Rossi, F Conti, M Eggiman, S Mach, A Di Mauro, M Guermandi, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 60-62, 2021 | 56 | 2021 |
Luca BeniniETH Zürich, Università di BolognaZweryfikowany adres z unibo.it
