| An FPGA implementation of information theoretic visual-saliency system and its optimization S Bae, YCP Cho, S Park, KM Irick, Y Jin, V Narayanan 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom …, 2011 | 44 | 2011 |
| Neural network accelerator including bidirectional processing element array L Chun-Gi, YS Kwon, C Kim, HM Kim, Y Jeongmin, J Chung, YCP Cho US Patent 11,507,429, 2022 | 28 | 2022 |
| Apparatus for processing convolutional neural network using systolic array and method thereof C Kim, YS Kwon, HM Kim, L Chun-Gi, YCP Cho, MS Choi, Y Jeongmin, ... US Patent App. 16/204,599, 2019 | 27 | 2019 |
| Function-safe vehicular ai processor with nano core-in-memory architecture Y Kwon, J Yang, YP Cho, KS Shin, J Chung, J Han, CG Lyuh, HM Kim, ... 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 19 | 2019 |
| Exploring Gabor filter implementations for visual cortex modeling on FPGA YCP Cho, S Bae, Y Jin, KM Irick, V Narayanan 2011 21st International Conference on Field Programmable Logic and …, 2011 | 16 | 2011 |
| Implementation of Yolo-v2 image recognition and other testbenches for a CNN accelerator C Kim, HM Kim, CG Lyuh, YCP Cho, J Yang, J Chung, KS Shin, JH Han, ... 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin …, 2019 | 14 | 2019 |
| AB9: A neural processor for inference acceleration YCP Cho, J Chung, J Yang, CG Lyuh, HM Kim, C Kim, J Ham, M Choi, ... ETRI Journal 42 (4), 491-504, 2020 | 12 | 2020 |
| Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems S Advani, N Chandramoorthy, K Swaminathan, K Irick, YCP Cho, ... 2014 IEEE 32nd International Conference on Computer Design (ICCD), 501-504, 2014 | 11 | 2014 |
| Chiplet heterogeneous-integration AI processor Y Kwon, J Han, YP Cho, J Kim, J Chung, J Choi, S Park, I Kim, H Kwon, ... 2023 International Conference on Electronics, Information, and Communication …, 2023 | 9 | 2023 |
| A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics J Han, Y Kwon, YCP Cho, HJ Yoo 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 313-316, 2017 | 9 | 2017 |
| A reconfigurable platform for the design and verification of domain-specific accelerators S Park, YCP Cho, KM Irick, V Narayanan 17th Asia and South Pacific Design Automation Conference, 108-113, 2012 | 9* | 2012 |
| Accelerating multiresolution Gabor feature extraction for real time vision applications YCP Cho, N Chandramoorthy, KM Irick, V Narayanan Journal of Signal Processing Systems 76, 149-168, 2014 | 6 | 2014 |
| Live demonstration: A neural processor for AI acceleration H Kim, J Chung, K Shin, CG Lyuh, HM Kim, C Kim, YCP Cho, J Yang, ... 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2021 | 5 | 2021 |
| AI 32TFLOPS autonomous driving processor on AI-ware with adaptive power saving Y Kwon, YP Cho, J Yang, J Chung, KS Shin, J Han, C Kim, CG Lyuh, ... 2019 International SoC Design Conference (ISOCC), 174-175, 2019 | 5 | 2019 |
| M3FPU: Multiformat matrix multiplication FPU architectures for neural network computations W Jeon, YCP Cho, HM Kim, H Kim, J Chung, J Kim, M Lee, CG Lyuh, ... 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 3 | 2022 |
| Method and apparatus for injecting fault and analyzing fault tolerance CHO Yong-Cheol, YS Kwon US Patent 10,489,520, 2019 | 3 | 2019 |
| Multiresolution Gabor feature extraction for real time applications YCP Cho, N Chandramoorthy, KM Irick, V Narayanan 2012 IEEE Workshop on Signal Processing Systems, 55-60, 2012 | 3 | 2012 |
| Processing element and operating method thereof in neural network YCP Cho, YS Kwon US Patent 11,494,623, 2022 | 2 | 2022 |
| A layer‐wise frequency scaling for a neural processing unit J Chung, HM Kim, K Shin, CG Lyuh, YCP Cho, J Han, Y Kwon, YH Gong, ... ETRI Journal 44 (5), 849-858, 2022 | 2 | 2022 |
| Neural network accelerator with systolic array structure J Chung, YS Kwon, L Chun-Gi, C Kim, HM Kim, Y Jeongmin, YCP Cho US Patent App. 16/677,835, 2020 | 2 | 2020 |
HyunMi KimSenior Engineer in Electronics and Telecommunications Research InstituteZweryfikowany adres z etri.re.kr
