| Can we build it: formal synthesis of control strategies for cooperative driver assistance systems W Damm, HJ Peter, J Rakow, B Westphal Mathematical Structures in Computer Science 23 (4), 676-725, 2013 | 36 | 2013 |
| Synthia: Verification and synthesis for timed automata HJ Peter, R Ehlers, R Mattmüller International Conference on Computer Aided Verification, 649-655, 2011 | 36 | 2011 |
| Fully symbolic timed model checking using constraint matrix diagrams R Ehlers, D Fass, M Gerke, HJ Peter 2010 31st IEEE Real-Time Systems Symposium, 360-371, 2010 | 29 | 2010 |
| Template-based controller synthesis for timed systems B Finkbeiner, HJ Peter International Conference on Tools and Algorithms for the Construction and …, 2012 | 28 | 2012 |
| Combining symbolic representations for solving timed games R Ehlers, R Mattmüller, HJ Peter International Conference on Formal Modeling and Analysis of Timed Systems …, 2010 | 22 | 2010 |
| Model checking the flexray physical layer protocol M Gerke, R Ehlers, B Finkbeiner, HJ Peter International Workshop on Formal Methods for Industrial Critical Systems …, 2010 | 20 | 2010 |
| Component-based abstraction refinement for timed controller synthesis HJ Peter, R Mattmüller 2009 30th IEEE Real-Time Systems Symposium, 364-374, 2009 | 15 | 2009 |
| Synthesising certificates in networks of timed automata B Finkbeiner, HJ Peter, S Schewe IET software 4 (3), 222-235, 2010 | 7 | 2010 |
| Making the right cut in model checking data-intensive timed systems R Ehlers, M Gerke, HJ Peter Formal Methods and Software Engineering: 12th International Conference on …, 2010 | 7 | 2010 |
| Conclusively verifying clock-domain crossings in very large hardware designs G Plassan, HJ Peter, K Morin-Allory, F Rahim, S Sarwary, D Borrione 2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016 | 6 | 2016 |
| Improving the efficiency of formal verification: the case of clock-domain crossings G Plassan, HJ Peter, K Morin-Allory, S Sarwary, D Borrione VLSI-SoC: System-on-Chip in the Nanoscale Era–Design, Verification and …, 2017 | 4 | 2017 |
| RESY: Requirement synthesis for compositional model checking B Finkbeiner, HJ Peter, S Schewe International Conference on Tools and Algorithms for the Construction and …, 2008 | 4 | 2008 |
| Formal clock network analysis, visualization, verification and generation MS Sarwary, HJ Peter, G Plassan, B Chakrabarti, MH Movahed-ezazi US Patent 10,599,800, 2020 | 2 | 2020 |
| The complexity of bounded synthesis for timed control with partial observability HJ Peter, B Finkbeiner International Conference on Formal Modeling and Analysis of Timed Systems …, 2012 | 1 | 2012 |
| FlexRay for Avionics: Automatic Verification with Parametric Physical Layers M Gerke, R Ehlers, B Finkbeiner, HJ Peter Infotech@ Aerospace 2012, 2583, 2012 | 1 | 2012 |
| IVER SITA S HJ Peter | 1 | |
| CONTROLLER PROGRAM SYNTHESIS HJ Peter SAARLAND UNIVERSITY, GERMANY, 2005 | | 2005 |