| Fuse circuitry to control the propagation delay of an IC DC McClure US Patent 5,428,311, 1995 | 115 | 1995 |
| Active hierarchical bitline memory architecture DC McClure US Patent 5,986,914, 1999 | 107 | 1999 |
| Column redundancy architecture for a read/write memory DC McClure, N Iyengar US Patent 5,257,229, 1993 | 95 | 1993 |
| Variable input threshold adjustment DC McClure US Patent 5,589,783, 1996 | 77 | 1996 |
| Semiconductor memory with multiplexed redundancy TA Coker, DC McClure US Patent 5,355,340, 1994 | 75 | 1994 |
| Fault detection for entire wafer stress test DC McClure US Patent 5,619,462, 1997 | 69 | 1997 |
| Circuit and method for setting the time duration of a write to a memory cell DC McClure US Patent 6,006,339, 1999 | 64 | 1999 |
| Method and apparatus for programming signal timing DC McClure US Patent 5,579,326, 1996 | 64 | 1996 |
| Semiconductor memory with inhibited test mode entry during power-up DC McClure, TA Coker US Patent 5,408,435, 1995 | 62 | 1995 |
| Dual dynamic sense amplifiers for a memory array DC McClure US Patent 5,455,802, 1995 | 59 | 1995 |
| Semiconductor memory with improved test mode DC McClure, TA Coker US Patent 5,265,100, 1993 | 59 | 1993 |
| Circuit for providing a compensated bias voltage DC McClure, TA Teel US Patent 5,568,084, 1996 | 57 | 1996 |
| Multiple clocked dynamic sense amplifier DC McClure US Patent 5,485,430, 1996 | 55 | 1996 |
| Semiconductor memory having improved latched repeaters for memory row line selection DC McClure US Patent 5,128,897, 1992 | 55 | 1992 |
| Semiconductor memory with sequenced latched row line repeaters WC Slemmer, DC McClure US Patent 5,124,951, 1992 | 54 | 1992 |
| Semiconductor memory with improved redundant sense amplifier control DC McClure US Patent 5,455,798, 1995 | 53 | 1995 |
| Precharging output driver circuit DC McClure, MA Lysinger, WC Slemmer US Patent 5,450,019, 1995 | 51 | 1995 |
| Redundancy decoder DC McClure US Patent 5,471,426, 1995 | 49 | 1995 |
| Integrated volatile and non-volatile memory DC McClure US Patent 6,781,916, 2004 | 48 | 2004 |
| Semiconductor memory with sequential clocked access codes for test mode entry WC Slemmer, TA Coker, DC McClure US Patent 5,072,138, 1991 | 47 | 1991 |
