| Designing fault-tolerant techniques for SRAM-based FPGAs FG de Lima Kastensmidt, G Neuberger, RF Hentschke, L Carro, R Reis IEEE Design & Test of Computers 21 (6), 552-562, 2004 | 176 | 2004 |
| Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy R Hentschke, F Marques, F Lima, L Carro, A Susin, R Reis Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 95-100, 2002 | 159 | 2002 |
| Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing R Hentschke, G Flach, F Pinto, R Reis Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006 | 31 | 2006 |
| Exact route matching algorithms for analog and mixed signal integrated circuits MM Ozdal, RF Hentschke Proceedings of the 2009 international Conference on Computer-Aided Design …, 2009 | 30 | 2009 |
| 3D-vias aware quadratic placement for 3D VLSI circuits R Hentschke, G Flach, F Pinto, R Reis IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 67-72, 2007 | 29 | 2007 |
| Improving simulated annealing placement by applying random and greedy mixed perturbations [IC layout] RF Hentschke, R Reis 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003 | 25 | 2003 |
| Maze routing steiner trees with effective critical sink optimization RF Hentschke, J Narasimham, MO Johann, RL Reis Proceedings of the 2007 international symposium on Physical design, 135-142, 2007 | 23 | 2007 |
| Algorithms for maze routing with exact matching constraints MM Ozdal, RF Hentschke IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 21 | 2013 |
| Maze routing algorithms with exact matching constraints for analog and mixed signal designs MM Ozdal, RF Hentschke Proceedings of the International Conference on Computer-Aided Design, 130-136, 2012 | 21 | 2012 |
| Maze routing Steiner trees with delay versus wire length tradeoff R Hentschke, J Narasimhan, M Johann, R Reis IEEE transactions on very large scale integration (VLSI) systems 17 (8 …, 2009 | 16 | 2009 |
| Methods and apparatus for providing flexible timing-driven routing trees RF Hentschke, MDO Johann, J Narasimhan, RADL Reis US Patent 8,095,904, 2012 | 15 | 2012 |
| Methods and apparatus for providing flexible timing-driven routing trees RF Hentschke, M de Oliveira Johann, J Narasimhan, RADL Reis US Patent 7,571,411, 2009 | 14 | 2009 |
| An algorithmic study of exact route matching for integrated circuits MM Ozdal, RF Hentschke IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 13 | 2011 |
| An algorithm for i/o pins partitioning targeting 3d vlsi integrated circuits S Sawicki, R Hentschke, M Johann, R Reis 2006 49th IEEE International Midwest Symposium on Circuits and Systems 2 …, 2006 | 12 | 2006 |
| Design space exploration with automatic generation of IP-based embedded software JCB de Mattos, L Brisolara, R Hentschke, L Carro, FR Wagner IFIP Working Conference on Distributed and Parallel Embedded Systems, 237-246, 2004 | 12 | 2004 |
| An algorithm for i/o partitioning targeting 3d circuits and its impact on 3d-vias R Hentschke, S Sawicki, M Johann, R Reis 2006 IFIP International Conference on Very Large Scale Integration, 128-133, 2006 | 10 | 2006 |
| Cell placement on graphics processing units G Flach, M Johann, R Hentschke, R Reis Proceedings of the 20th annual conference on Integrated circuits and systems …, 2007 | 9 | 2007 |
| A 3d-via legalization algorithm for 3d vlsi circuits and its impact on wire length R Hentschke, R Reis 2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2036-2039, 2007 | 9 | 2007 |
| Algorithms for wire length improvement of vlsi circuits with concern to critical paths RF Hentschke | 9 | 2007 |
| Algoritmos para o Posicionamento de Células em Circuitos VLSI RF Hentschke | 7 | 2002 |
