| Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs Y Zhang, X Wang, Y Li, AK Jones, Y Chen | 107* | |
| Compiler-assisted data distribution for chip multiprocessors Y Li, A Abousamra, R Melhem, AK Jones Proceedings of the 19th international conference on Parallel architectures …, 2010 | 65 | 2010 |
| Going vertical in memory management: Handling multiplicity by multi-policy L Liu, Y Li, Z Cui, Y Bao, M Chen, C Wu Acm Sigarch Computer Architecture News 42 (3), 169-180, 2014 | 58 | 2014 |
| A software approach for combating asymmetries of non-volatile memories Y Li, Y Chen, AK Jones Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 58 | 2012 |
| Read performance: The newest barrier in scaled STT-RAM AKJ Y Zhang, Y Li, Z Sun, H Li, Y Chen IEEE, 2015 | 55* | 2015 |
| Practically private: Enabling high performance cmps through compiler-assisted data classification Y Li, R Melhem, AK Jones Proceedings of the 21st international conference on Parallel architectures …, 2012 | 46 | 2012 |
| Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random HYCW Lei Liu, Yong Li, Chen Ding IEEE Transactions on Computers, 2015 | 39 | 2015 |
| Multilane Racetrack Caches: Improving Efficiency Through Compression and Independent Shifting AKJ Haifeng Xu, Yong Li, Rami Melhem | 37* | |
| BPM/BPM+ Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems L Liu, Z Cui, Y Li, Y Bao, M Chen, C Wu ACM Transactions on Architecture and Code Optimization (TACO) 11 (1), 1-28, 2014 | 28 | 2014 |
| Memos: A full hierarchy hybrid memory management framework L Liu, H Yang, Y Li, M Xie, L Li, C Wu 2016 IEEE 34th International Conference on Computer Design (ICCD), 368-371, 2016 | 25 | 2016 |
| C1C: A configurable, compiler-guided STT-RAM L1 cache Y Li, Y Zhang, H Li, Y Chen, AK Jones ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-22, 2013 | 23 | 2013 |
| Prefetching techniques for STT-RAM based last-level cache in CMP systems M Mao, G Sun, Y Li, AK Jones, Y Chen Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, 67-72, 2014 | 21 | 2014 |
| PS-TLB: Leveraging page classification information for fast, scalable and efficient translation for future CMPs Y Li, R Melhem, AK Jones ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-21, 2013 | 20 | 2013 |
| Space oblivious compression: Power reduction for non-volatile main memories Y Li, H Xu, R Melhem, AK Jones Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 217-220, 2015 | 16 | 2015 |
| STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures X Liu, Y Li, Y Zhang, AK Jones, Y Chen 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 355-360, 2014 | 13 | 2014 |
| Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors Y Li, A Abousamra, R Melhem, A Jones Parallel and Distributed Systems, IEEE Transactions on, 1-1, 2011 | 9 | 2011 |
| Cross-layer techniques for optimizing systems utilizing memories with asymmetric access characteristics Y Li, AK Jones 2012 IEEE Computer Society Annual Symposium on VLSI, 404-409, 2012 | 8 | 2012 |
| A practical data classification framework for scalable and high performance chip-multiprocessors Y Li, R Melhem, AK Jones IEEE Transactions on Computers 63 (12), 2905-2918, 2013 | 6 | 2013 |
| Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors Y Li, R Melhem, A Jones IEEE IEEE Computer Architecture Letters, 2011 | 6 | 2011 |
| Existence and ergodicity for the two-dimensional stochastic Boussinesq equation Y Li, C Trenchea Int. J. Numer. Anal. Model 15 (4-5), 715-728, 2018 | 5 | 2018 |
Rami MelhemThe university of PittsburghVerifisert e-postadresse på cs.pitt.edu