| A low-power, high-performance, 1024-point FFT processor BM Baas IEEE Journal of Solid-State Circuits 34 (3), 380-387, 1999 | 474 | 1999 |
| Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm A Stillmaker, B Baas Integration 58, 74-81, 2017 | 397 | 2017 |
| A 167-processor computational platform in 65 nm CMOS DN Truong, WH Cheng, T Mohsenin, Z Yu, AT Jacobson, G Landge, ... IEEE Journal of Solid-State Circuits 44 (4), 1130-1144, 2009 | 315 | 2009 |
| An Integrated 802.11a Baseband and MAC Processor J Thomson, B Baas, EM Cooper, JM Gilbert, G Hsieh, P Husted, ... Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC …, 2002 | 152 | 2002 |
| Parallel AES encryption engines for many-core processor arrays B Liu, BM Baas IEEE Transactions on Computers 62 (3), 536-547, 2013 | 145 | 2013 |
| KiloCore: A 32-nm 1000-processor computational array B Bohnenstiehl, A Stillmaker, JJ Pimentel, T Andreas, B Liu, AT Tran, ... IEEE Journal of Solid-State Circuits 52 (4), 891-902, 2017 | 132 | 2017 |
| A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders T Mohsenin, DN Truong, BM Baas IEEE Transactions on Circuits and Systems I: Regular Papers 57 (5), 1048-1061, 2010 | 129 | 2010 |
| An asynchronous array of simple processors for DSP applications Z Yu, M Meeuwsen, R Apperson, O Sattari, M Lai, J Webb, E Work, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 122 | 2006 |
| AsAP: An asynchronous array of simple processors Z Yu, MJ Meeuwsen, RW Apperson, O Sattari, M Lai, JW Webb, EW Work, ... IEEE Journal of Solid-State Circuits 43 (3), 695-705, 2008 | 115 | 2008 |
| A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains RW Apperson, Z Yu, MJ Meeuwsen, T Mohsenin, BM Baas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (10 …, 2007 | 107 | 2007 |
| A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling D Truong, W Cheng, T Mohsenin, Z Yu, T Jacobson, G Landge, ... 2008 IEEE Symposium on VLSI Circuits, 22-23, 2008 | 90 | 2008 |
| A 5.8 pj/op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array B Bohnenstiehl, A Stillmaker, J Pimentel, T Andreas, B Liu, A Tran, ... 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 87 | 2016 |
| Dynamic voltage and frequency scaling circuits with two supply voltages WH Cheng, BM Baas 2008 IEEE International Symposium on Circuits and Systems, 1236-1239, 2008 | 80 | 2008 |
| Achieving high-performance on-chip networks with shared-buffer routers AT Tran, BM Baas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (6 …, 2013 | 67 | 2013 |
| NoCTweak: a highly parameterizable simulator for early exploration of performance and energy of networks on-chip AT Tran, B Baas VLSI Computation Lab, ECE Department, University of California, Davis, Tech …, 2012 | 62 | 2012 |
| DeepScaleTool: A tool for the accurate estimation of technology scaling in the deep-submicron era S Sarangi, B Baas 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 60 | 2021 |
| The design of a reconfigurable continuous-flow mixed-radix FFT processor AT Jacobson, DN Truong, BM Baas 2009 IEEE International Symposium on Circuits and Systems, 1133-1136, 2009 | 58 | 2009 |
| Toward more accurate scaling estimates of cmos circuits from 180 nm to 22 nm A Stillmaker, Z Xiao, B Baas VLSI Computation Lab, ECE Department, University of California, Davis, Tech …, 2011 | 57 | 2011 |
| High performance, energy efficiency, and scalability with GALS chip multiprocessors Z Yu, BM Baas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (1), 66-79, 2008 | 57 | 2008 |
| An approach to low-power, high-performance, fast Fourier transform processor design BM Baas Stanford University, 1999 | 57 | 1999 |
Tinoosh MohseninJohns Hopkins UniversityVerifisert e-postadresse på jhu.edu