| Bi-directional adaptive clocking circuit supporting a wide frequency range W Shan, J Yang, L Shi US Patent 11,139,805, 2021 | 139 | 2021 |
| 14.1 A 510nW 0.41 V low-memory low-computation keyword-spotting chip using serial FFT-based MFCC and binarized depthwise separable convolutional neural network in 28nm CMOS W Shan, M Yang, J Xu, Y Lu, S Zhang, T Wang, J Yang, L Shi, M Seok 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 230-232, 2020 | 79 | 2020 |
| A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS W Shan, M Yang, T Wang, Y Lu, H Cai, L Zhu, J Xu, C Wu, L Shi, J Yang IEEE Journal of Solid-State Circuits 56 (1), 151-164, 2021 | 68 | 2021 |
| A secure reconfigurable crypto IC with countermeasures against SPA, DPA, and EMA W Shan, X Fu, Z Xu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 60 | 2015 |
| A 28nm 64-kb 31.6-TFLOPS/W digital-domain floating-point-computing-unit and double-bit 6T-SRAM computing-in-memory macro for floating-point CNNs A Guo, X Si, X Chen, F Dong, X Pu, D Li, Y Zhou, L Ren, Y Xue, X Dong, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 128-130, 2023 | 49 | 2023 |
| Analog circuit implementation of a variable universe adaptive fuzzy logic controller W Shan, Y Ma, RW Newcomb, D Jin IEEE Transactions on Circuits and Systems II: Express Briefs 55 (10), 976-980, 2008 | 40 | 2008 |
| 33.4 A 28nm 2Mb STT-MRAM computing-in-memory macro with a refined bit-cell and 22.4-41.5 TOPS/W for AI inference H Cai, Z Bian, Y Hou, Y Zhou, Y Guo, X Tian, B Liu, X Si, Z Wang, J Yang, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 500-502, 2023 | 39 | 2023 |
| Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction MS Minhao Yang, Hongjie Liu, Weiwei Shan, Jun Zhang, Ilya Kiselev, Sang Joon ... IEEE J. Solid-State Circuits, 2021 | 38 | 2021 |
| Machine learning based side-channel-attack countermeasure with hamming-distance redistribution and its application on advanced encryption standard SZYH Weiwei Shan Electronics Letters 53 (14), 926-928, 2017 | 36 | 2017 |
| Machine learning assisted side-channel-attack countermeasure and its application on a 28-nm AES circuit W Shan, S Zhang, J Xu, M Lu, L Shi, J Yang IEEE Journal of Solid-State Circuits 55 (3), 794-804, 2019 | 32 | 2019 |
| TG-SPP: A one-transmission-gate short-path padding for wide-voltage-range resilient circuits in 28-nm CMOS W Shan, W Dai, C Zhang, H Cai, P Liu, J Yang, L Shi IEEE Journal of Solid-State Circuits 55 (5), 1422-1436, 2019 | 27 | 2019 |
| An ultra-energy-efficient and high accuracy ECG classification processor with SNN inference assisted by on-chip ANN learning R Mao, S Li, Z Zhang, Z Xia, J Xiao, Z Zhu, J Liu, W Shan, L Chang, ... IEEE Transactions on Biomedical Circuits and Systems 16 (5), 832-841, 2022 | 26 | 2022 |
| A compact, lightweight and low-cost 8-bit datapath AES circuit for IOT applications in 28nm CMOS M Lu, A Fan, J Xu, W Shan 2018 17th IEEE International Conference On Trust, Security And Privacy In …, 2018 | 24 | 2018 |
| Dynamic voltage scaling system based on on-chip monitoring and voltage prediction L Shi, W Shan, J Yang, H Gu, X Liu, Y Zhang US Patent 8,909,999, 2014 | 24 | 2014 |
| Timing error prediction AVFS with detection window tuning for wide-operating-range ICs WDJY Weiwei Shan, Xinchao Shang, Longxing Shi IEEE Transactions on Circuits and Systems--II: Express Briefs 65 (7), 933- 937, 2018 | 20* | 2018 |
| A wide-voltage-range half-path timing error-detection system with a 9-transistor transition-detector in 40-nm CMOS W Shan, X Shang, X Wan, H Cai, C Zhang, J Yang IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2288-2297, 2019 | 19 | 2019 |
| Gain scheduling pitch control design for active tower damping and 3p harmonic reduction W Shan, M Shan | 19 | 2013 |
| In-situ Timing Monitor based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications JY Weiwei Shan, Longxing Shi IEEE access 5, 15831 - 15838, 2017 | 18 | 2017 |
| An improved timing error prediction monitor for wide adaptive frequency scaling W Shan, X Liu, M Lu, S Shao, Z Cai, J Yang IEICE Electronics Express 14 (21), 20170808-20170808, 2017 | 17 | 2017 |
| A side-channel analysis resistant reconfigurable cryptographic coprocessor supporting multiple block cipher algorithms W Shan, L Shi, X Fu, X Zhang, C Tian, Z Xu, J Yang, J Li Proceedings of the 51st annual design automation conference, 1-6, 2014 | 17 | 2014 |
Hao CaiSoutheast University, Nanjing, ChinaVerifisert e-postadresse på telecom-paristech.fr