| Cycle-static dataflow G Bilsen, M Engels, R Lauwereins, J Peperstraete IEEE Transactions on signal processing 44 (2), 397-408, 1996 | 888 | 1996 |
| ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins Field Programmable Logic and Application: 13th International Conference, FPL …, 2003 | 860 | 2003 |
| Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins IEE Proceedings-Computers and Digital Techniques 150 (5), 255-261, 2003 | 325 | 2003 |
| DRESC: A retargetable compiler for coarse-grained reconfigurable architectures B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins 2002 IEEE International Conference on Field-Programmable Technology, 2002 …, 2002 | 295 | 2002 |
| Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs T Marescaux, A Bartic, D Verkest, S Vernalde, R Lauwereins Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002 | 266 | 2002 |
| Architecture exploration for a reconfigurable architecture template B Mei, A Lambrechts, JY Mignolet, D Verkest, R Lauwereins IEEE Design & Test of Computers 22 (2), 90-101, 2005 | 243 | 2005 |
| Energy-aware runtime scheduling for embedded-multiprocessor SOCs P Yang, C Wong, P Marchal, F Catthoor, D Desmet, D Verkest, ... IEEE Design & Test of Computers 18 (05), 46-58, 2001 | 203 | 2001 |
| Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip JY Mignolet, V Nollet, P Coene, D Verkest, S Vernalde, R Lauwereins 2003 Design, Automation and Test in Europe Conference and Exhibition, 986-991, 2003 | 197 | 2003 |
| Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: A case study B Mei, S Vernalde, D Verkest, R Lauwereins Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 193 | 2004 |
| Grape-II: A system-level prototyping environment for DSP applications R Lauwereins, M Engels, M Ade, JA Peperstraete Computer 28 (2), 35-43, 1995 | 187 | 1995 |
| Designing an operating system for a heterogeneous reconfigurable SoC V Nollet, P Coene, D Verkest, S Vernalde, R Lauwereins Proceedings International Parallel and Distributed Processing Symposium, 7 pp., 2003 | 153 | 2003 |
| Networks on chip as hardware components of an OS for reconfigurable systems T Marescaux, JY Mignolet, A Bartic, W Moffat, D Verkest, S Vernalde, ... Field Programmable Logic and Application: 13th International Conference, FPL …, 2003 | 131 | 2003 |
| Reconfigurable instruction set processors from a hardware/software perspective F Barat, R Lauwereins, G Deconinck IEEE Transactions on Software Engineering 28 (9), 847-862, 2002 | 129 | 2002 |
| Topology adaptive network-on-chip design and implementation TA Bartic, JY Mignolet, V Nollet, T Marescaux, D Verkest, S Vernalde, ... IEE Proceedings-Computers and Digital Techniques 152 (4), 467-472, 2005 | 118 | 2005 |
| Managing dynamic concurrent tasks in embedded real-time multimedia systems P Yang, P Marchal, C Wong, S Himpe, F Catthoor, P David, J Vounckx, ... Proceedings of the 15th international symposium on System Synthesis, 112-119, 2002 | 108 | 2002 |
| Task concurrency management design method F Catthoor, P Yang, C Wong, P Marchal, A Prayati, N Cossement, ... US Patent 7,234,126, 2007 | 103 | 2007 |
| Reconfigurable instruction set processors: a survey F Barat, R Lauwereins Proceedings 11th International Workshop on Rapid System Prototyping. RSP …, 2000 | 101 | 2000 |
| Grape: A CASE tool for digital signal parallel processing R Lauwereins, M Engels, J Peperstraete, E Steegmans, ... IEEE ASSP Magazine 7 (2), 32-43, 1990 | 98 | 1990 |
| Run-time support for heterogeneous multitasking on reconfigurable SoCs T Marescaux, V Nollet, JY Mignolet, A Bartic, W Moffat, P Avasare, ... Integration 38 (1), 107-130, 2004 | 94 | 2004 |
| Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets M Adé, R Lauwereins, JA Peperstraete Proceedings of the 34th annual design automation conference, 64-69, 1997 | 93 | 1997 |
