| Switching theory for logic synthesis T Sasao Springer Science & Business Media, 2012 | 617 | 2012 |
| Representations of discrete functions T Sasao, M Fujita Kluwer Academic, 1996 | 399 | 1996 |
| Logic synthesis and optimization T Sasao Kluwer Academic Publishers, 1993 | 394 | 1993 |
| On the complexity of mod-2l sum PLA's T Sasao, P Besslich IEEE Transactions on Computers 39 (2), 262-266, 1990 | 282 | 1990 |
| Logic synthesis and verification S Hassoun, T Sasao Springer Science & Business Media, 2001 | 227 | 2001 |
| EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions T Sasao IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 221 | 1993 |
| Input variable assignment and output phase optimization of PLA's Sasao IEEE Transactions on Computers 100 (10), 879-894, 1984 | 197 | 1984 |
| FPGA design by generalized functional decomposition T Sasao Logic synthesis and optimization, 233-258, 1993 | 153 | 1993 |
| Easily testable realizations for generalized Reed-Muller expressions T Sasao IEEE transactions on computers 46 (6), 709-716, 1997 | 127 | 1997 |
| Memory-based logic synthesis T Sasao Springer Science & Business Media, 2011 | 126 | 2011 |
| Multiple-valued decomposition of generalized Boolean functions and the complexity of programmable logic arrays Sasao IEEE Transactions on computers 100 (9), 635-643, 1981 | 122 | 1981 |
| AND-EXOR expressions and their optimization T Sasao Logic synthesis and optimization, 287-312, 1993 | 119 | 1993 |
| Representations of logic functions using EXOR operators T Sasao Representations of discrete functions, 29-54, 1996 | 104 | 1996 |
| On the optimal design of multiple-valued PLAs T Sasao IEEE Transactions on Computers 38 (4), 582-592, 1989 | 99 | 1989 |
| A method to represent multiple-output switching functions by using multi-valued decision diagrams T Sasao, JT Butler Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic …, 1996 | 97 | 1996 |
| Numerical function generators using LUT cascades T Sasao, S Nagayama, JT Butler IEEE Transactions on Computers 56 (6), 826-838, 2007 | 93 | 2007 |
| A cascade realization of multiple-output function for reconfigurable hardware T Sasao, M Matsuura, Y Iguchi International Workshop on Logic and Synthesis (IWLS01), 12-15, 2001 | 93 | 2001 |
| Selection of potentially testable path delay faults for test generation A Murakami, S Kajihara, T Sasao, I Pomeranz, SM Reddy Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000 | 92 | 2000 |
| Ternary decision diagrams. Survey T Sasao Proceedings 1997 27th International Symposium on Multiple-Valued Logic, 241-250, 1997 | 85 | 1997 |
| A deep convolutional neural network based on nested residue number system H Nakahara, T Sasao 2015 25th International Conference on Field Programmable Logic and …, 2015 | 83 | 2015 |
Shinobu NagayamaHiroshima City UniversityVerifisert e-postadresse på hiroshima-cu.ac.jp