| Arithmetic core generation using bit heaps N Brunie, F De Dinechin, M Istoan, G Sergent, K Illyes, B Popa 2013 23rd International Conference on Field programmable Logic and …, 2013 | 60 | 2013 |
| Hardware implementations of fixed-point Atan2 F De Dinechin, M Istoan 2015 IEEE 22nd Symposium on Computer Arithmetic, 34-41, 2015 | 53 | 2015 |
| Fixed-point trigonometric functions on FPGAs F De Dinechin, M Istoan, G Sergent ACM SIGARCH Computer Architecture News 41 (5), 83-88, 2014 | 38 | 2014 |
| Resource optimal design of large multipliers for FPGAs M Kumm, J Kappauf, M Istoan, P Zipf 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH), 131-138, 2017 | 33 | 2017 |
| Towards hardware IIR filters computing just right: Direct form I case study A Volkova, M Istoan, F De Dinechin, T Hilaire IEEE Transactions on Computers 68 (4), 597-608, 2018 | 30 | 2018 |
| Sum-of-product architectures computing just right F De Dinechin, M Istoan, A Massouri 2014 IEEE 25th International Conference on Application-Specific Systems …, 2014 | 19 | 2014 |
| Automating the pipeline of arithmetic datapaths M Iştoan, F De Dinechin Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 17 | 2017 |
| Fixed-point implementations of the reciprocal, square root and reciprocal square root functions M Istoan, B Pasca | 9 | 2015 |
| A high throughput polynomial and rational function approximations evaluator N Brisebarre, G Constantinides, M Ercezovac, SI Filip, M Istoan, JM Muller 2018 IEEE 25th Symposium on Computer Arithmetic (ARITH), 99-106, 2018 | 5 | 2018 |
| Flexible fixed-point function generation for FPGAs M Iştoan, B Pasca 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH), 123-130, 2017 | 5 | 2017 |
| A study of the effects and benefits of custom-precision mathematical libraries for HPC codes E Brun, D Defour, P de Oliveira Castro, M Iştoan, D Mancusi, E Petit, ... IEEE Transactions on Emerging Topics in Computing 9 (3), 1467-1478, 2021 | 4 | 2021 |
| Custom-precision mathematical library explorations for code profiling and optimization D Defour, P de Oliveira Castro, M Iştoan, E Petit 2020 IEEE 27th Symposium on Computer Arithmetic (ARITH), 121-124, 2020 | 3 | 2020 |
| Shadow computation with BFloat16 to compute numerical accuracy D Defour, P de Oliveira Castro, M Istoan, E Petit | 2 | 2021 |
| Arithmetic around the bit heap F De Dinechin, M Istoan, G Sergent, K Illyes, B Popa, N Brunie Technical report, Oct, 2012 | 2 | 2012 |
| Hardware IIR Filters: Direct Form I Computing Just Right F de Dinechin, T Hilaire, M Istoan, A Volkova Jul. 2017, technical report available online http://hal. upmc. fr/hal-01561052, 0 | 2 | |
| Shadow computation with BFloat16 to estimate the numerical accuracy of summations D Defour, P de Oliveira Castro, M Iştoan, E Petit 2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), 33-36, 2021 | 1 | 2021 |
| High-performance coarse operators for FPGA-based computing MV Istoan Université de Lyon, 2017 | 1 | 2017 |
| An open-access Web-based sociohydrological model platform for improved water security and user decision-making J O'Keeffe, S Moulds, J Davis, S Fleming, M Istoan AGU Fall Meeting Abstracts 2018, PA23G-1059, 2018 | | 2018 |
| Automatic generation of hardware FIR filters from a frequency domain specification SI Filip, M Istoan, F de Dinechin, N Brisebarre | | 2017 |
| Pipeline automatique d’opérateurs dans FloPoCo 5.0 M Istoan, F de Dinechin COMPAS'2016: Conférence d’informatique en Parallélisme, Architecture et Système, 2016 | | 2016 |
Florent de Dinechinprofessor, INSA-LyonVerifisert e-postadresse på insa-lyon.fr
