| A study of tapered 3-D TSVs for power and thermal integrity A Todri, S Kundu, P Girard, A Bosio, L Dilillo, A Virazel IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 306-319, 2012 | 93 | 2012 |
| Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution L Dilillo, P Girard, S Pravossoudovitch, A Virazel, S Borri, M Hage-Hassan Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004., 140-145, 2004 | 89 | 2004 |
| Advanced test methods for SRAMs: effective solutions for dynamic fault detection in nanoscaled technologies A Bosio, L Dilillo, P Girard, S Pravossoudovitch, A Virazel Springer Science & Business Media, 2009 | 85 | 2009 |
| Resistive-open defects in embedded-SRAM core cells: analysis and march test solution L Dilillo, P Girard, S Pravossoudovitch, A Virazel, S Borri, M Hage-Hassan 13th Asian test symposium, 266-271, 2004 | 85 | 2004 |
| Using TMR architectures for yield improvement J Vial, A Bosio, P Girard, C Landrault, S Pravossoudovitch, A Virazel 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008 | 78 | 2008 |
| Design of routing-constrained low power scan chains Y Bonhomme, P Girard, L Guiller, C Landrault, S Pravossoudovitch, ... Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 75 | 2004 |
| Multiple cell upset classification in commercial SRAMs G Tsiligiannis, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Todri, ... IEEE Transactions on Nuclear Science 61 (4), 1747-1754, 2014 | 71 | 2014 |
| Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics N Badereddine, P Girard, S Pravossoudovitch, C Landrault, A Virazel, ... International Conference on Design and Test of Integrated Systems in …, 2006 | 70 | 2006 |
| Defect-oriented dynamic fault models for embedded-SRAMs S Borri, M Hage-Hassan, P Girard, S Pravossoudovitch, A Virazel The Eighth IEEE European Test Workshop, 2003. Proceedings., 23-28, 2003 | 57 | 2003 |
| Testing a commercial MRAM under neutron and alpha radiation in dynamic mode G Tsiligiannis, L Dilillo, A Bosio, P Girard, A Todri, A Virazel, SS McClure, ... IEEE Transactions on Nuclear Science 60 (4), 2617-2622, 2013 | 49 | 2013 |
| High defect coverage with low-power test sequences in a BIST environment P Girard, C Landrault, S Pravossoudovitch, A Virazel, HJ Wunderlich IEEE Design & Test of Computers 19 (5), 44-52, 2002 | 49 | 2002 |
| Analysis of dynamic faults in embedded-SRAMs: Implications for memory test S Borri, M Hage-Hassan, L Dilillo, P Girard, S Pravossoudovitch, A Virazel Journal of Electronic Testing 21, 169-179, 2005 | 47 | 2005 |
| Data retention fault in SRAM memories: Analysis and detection procedures L Dilillo, P Girard, S Pravossoudovitch, A Virazel, MB Hage-Hassan 23rd IEEE VLSI Test Symposium (VTS'05), 183-188, 2005 | 45 | 2005 |
| Derric: A tool for unified logic diagnosis A Rousset, A Bosio, P Girard, C Landrault, S Pravossoudovitch, A Virazel 12th IEEE European Test Symposium (ETS'07), 13-20, 2007 | 43 | 2007 |
| Efficient march test procedure for dynamic read destructive fault detection in SRAM memories L Dilillo, P Girard, S Pravossoudovitch, A Virazel, S Borri, M Hage-Hassan Journal of Electronic Testing 21 (5), 551-561, 2005 | 42 | 2005 |
| A survey of test and reliability solutions for magnetic random access memories P Girard, Y Cheng, A Virazel, W Zhao, R Bishnoi, MB Tahoori Proceedings of the IEEE 109 (2), 149-169, 2020 | 41 | 2020 |
| Dynamic test methods for COTS SRAMs G Tsiligiannis, L Dilillo, V Gupta, A Bosio, P Girard, A Virazel, H Puchner, ... IEEE Transactions on Nuclear Science 61 (6), 3095-3102, 2014 | 40 | 2014 |
| Delay fault testing: Choosing between random SIC and random MIC test sequences A Virazel, R David, P Girard, C Landrault, S Pravossoudovitch Journal of Electronic Testing 17 (3), 233-241, 2001 | 40 | 2001 |
| Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 μm and 90 nm technologies L Dilillo, P Girard, S Pravossoudovitch, A Virazel, M Bastian Proceedings of the 42nd annual Design Automation Conference, 857-862, 2005 | 36 | 2005 |
| A functional power evaluation flow for defining test power limits during at-speed delay testing M Valka, A Bosio, L Dilillo, P Girard, S Pravossoudovitch, A Virazel, ... 2011 Sixteenth IEEE European Test Symposium, 153-158, 2011 | 35 | 2011 |
Patrick GirardLIRMMVerifisert e-postadresse på lirmm.fr