A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ...
IEEE Journal of Solid-State Circuits 50 (1), 68-80, 2014
164 2014 A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB AT Narayanan, M Katsuragi, K Kimura, S Kondo, KK Tokgoz, K Nakata, ...
IEEE Journal of Solid-State Circuits 51 (7), 1630-1640, 2016
138 2016 A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration A Musa, W Deng, T Siriburanon, M Miyahara, K Okada, A Matsuzawa
IEEE Journal of Solid-State Circuits 49 (1), 50-60, 2014
132 2014 Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing W Deng, K Okada, A Matsuzawa
IEEE Journal of Solid-State Circuits 2 (48), 429-440, 2013
121 2013 A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11 ad T Siriburanon, S Kondo, M Katsuragi, H Liu, K Kimura, W Deng, K Okada, ...
IEEE Journal of Solid-State Circuits 51 (5), 1246-1260, 2016
113 2016 A CMOS 76–81-GHz 2-TX 3-RX FMCW radar transceiver based on mixed-mode PLL chirp generator T Ma, W Deng, Z Chen, J Wu, W Zheng, S Wang, N Qi, Y Liu, B Chi
IEEE Journal of Solid-State Circuits 55 (2), 233-248, 2019
88 2019 A 2.2 GHz-242 dB-FOM 4.2 mW ADC-PLL using digital sub-sampling architecture T Siriburanon, S Kondo, K Kimura, T Ueno, S Kawashima, T Kaneko, ...
IEEE Journal of Solid-State Circuits 51 (6), 1385-1397, 2016
86 2016 A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers W Deng, T Siriburanon, A Musa, K Okada, A Matsuzawa
IEEE Journal of Solid-State Circuits 7 (48), 1710-1720, 2013
76 2013 14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
71 2015 A Sub-mW Fractional- H Liu, D Tang, Z Sun, W Deng, HC Ngo, K Okada
IEEE Journal of Solid-State Circuits 53 (12), 3540-3552, 2018
70 2018 15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
70 2014 A 265- H Liu, Z Sun, H Huang, W Deng, T Siriburanon, J Pang, Y Wang, R Wu, ...
IEEE Journal of Solid-State Circuits 54 (12), 3478-3492, 2019
68 2019 An ADPLL-centric bluetooth low-energy transceiver with 2.3 mW interference-tolerant hybrid-loop receiver and 2.9 mW single-point polar transmitter in 65nm CMOS H Liu, Z Sun, D Tang, H Huang, T Kaneko, W Deng, R Wu, K Okada, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 444-446, 2018
65 2018 A 0.022mm2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits W Deng, A Musa, T Siriburanon, M Miyahara, K Okada, A Matsuzawa
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
55 2013 A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of− 246dB for IoT applications in 65nm CMOS H Liu, D Tang, Z Sun, W Deng, HC Ngo, K Okada, A Matsuzawa
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 246-248, 2018
52 2018 A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators T Siriburanon, T Ueno, K Kimura, S Kondo, W Deng, K Okada, ...
2014 IEEE radio frequency integrated circuits symposium, 105-108, 2014
45 2014 A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular T Siriburanon, H Liu, K Nakata, W Deng, JH Son, DY Lee, K Okada, ...
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
42 2015 A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration B Liu, Y Zhang, J Qiu, HC Ngo, W Deng, K Nakata, T Yoshioka, J Emmei, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 603-616, 2020
41 2020 A DPLL-centric Bluetooth low-energy transceiver with a 2.3-mW interference-tolerant hybrid-loop receiver in 65-nm CMOS H Liu, Z Sun, D Tang, H Huang, T Kaneko, Z Chen, W Deng, R Wu, ...
IEEE Journal of Solid-State Circuits 53 (12), 3672-3687, 2018
41 2018 A 39GHz 64-element phased-array CMOS transceiver with built-in calibration for large-array 5G NR Y Wang, R Wu, J Pang, D You, AA Fadila, R Saengchan, X Fu, ...
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 279-282, 2019
40 2019 
Kenichi OkadaInstitute of Science Tokyo (formerly Tokyo Institute of Technology)Verifisert e-postadresse på ee.e.titech.ac.jp