| DRAM circuit design: fundamental and high-speed topics B Keeth, RJ Baker, B Johnson, F Lin John Wiley & Sons, 2007 | 267 | 2007 |
| A register-controlled symmetrical DLL for double-data-rate DRAM F Lin, J Miller, A Schoenfeld, M Ma, RJ Baker IEEE Journal of Solid-State Circuits 34 (4), 565-568, 1999 | 100 | 1999 |
| Digital dual-loop DLL design using coarse and fine loops RJ Baker, F Lin US Patent 6,445,231, 2002 | 91 | 2002 |
| Method and apparatus for improving stability and lock time for synchronous circuits F Lin, JB Johnson US Patent 6,839,301, 2005 | 83* | 2005 |
| Method and system for delay control in synchronization circuits F Lin, B Keeth, B Johnson US Patent 6,836,166, 2004 | 78 | 2004 |
| Capture clock generator using master and slave delay locked loops F Lin US Patent 6,839,860, 2005 | 67 | 2005 |
| Methods and apparatus for duty cycle control F Lin US Patent 6,940,328, 2005 | 62 | 2005 |
| Phase detector for all-digital phase locked and delay locked loops F Lin, RJ Baker US Patent 6,779,126, 2004 | 58 | 2004 |
| Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM B Johnson, B Keeth, F Lin US Patent 6,930,955, 2005 | 57 | 2005 |
| Method and apparatus for setting and compensating read latency in a high speed DRAM B Keeth, B Johnson, F Lin US Patent 6,687,185, 2004 | 56 | 2004 |
| Centralizing the lock point of a synchronous circuit FD Lin US Patent 7,098,714, 2006 | 55 | 2006 |
| Digital dual-loop DLL design using coarse and fine loops RJ Baker, F Lin US Patent 6,774,690, 2004 | 54 | 2004 |
| Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM JB Johnson, B Keeth, FD Lin US Patent 7,065,001, 2006 | 50 | 2006 |
| System and method to improve the efficiency of synchronous mirror delays and delay locked loops F Lin US Patent 6,798,259, 2004 | 50 | 2004 |
| Phase splitter using digital delay locked loops F Lin, RJ Baker US Patent 6,950,487, 2005 | 45 | 2005 |
| Interleaved delay line for phase locked and delay locked loops F Lin US Patent 6,868,504, 2005 | 43 | 2005 |
| A wide-range mixed-mode DLL for a combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM F Lin, RA Royer, B Johnson, B Keeth IEEE Journal of Solid-State Circuits 43 (3), 631-641, 2008 | 38 | 2008 |
| Interleaved delay line for phase locked and delay locked loops F Lin US Patent 7,103,791, 2006 | 36 | 2006 |
| Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM JB Johnson, B Keeth, FD Lin US Patent 7,660,187, 2010 | 34 | 2010 |
| Phase detector and method providing rapid locking of delay-lock loops F Lin US Patent 7,428,284, 2008 | 30 | 2008 |
R. Jacob Bakerprofessor emeritus of electrical and computer engineeringunlv.edu의 이메일 확인됨