| Gbit/s lossless data compression hardware JL Núñez, S Jones IEEE Transactions on very large scale integration (VLSI) systems 11 (3), 499-510, 2003 | 112 | 2003 |
| Remaining useful life estimation using long short-term memory neural networks and deep fusion Y Zhang, P Hutchinson, NAJ Lieven, J Nunez-Yanez IEEE access 8, 19033-19045, 2020 | 73 | 2020 |
| Video super-resolution using generalized Gaussian Markov random fields J Chen, J Nunez-Yanez, A Achim IEEE Signal Processing Letters 19 (2), 63-66, 2011 | 55 | 2011 |
| Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H. 264 advanced video codec YL Nunez-Yanez, VA Chouliaras, D Alfonso, FS Rovati IEEE Transactions on Consumer Electronics 52 (2), 590-597, 2006 | 53 | 2006 |
| Energy optimization in commercial FPGAs with voltage, frequency and logic scaling JL Nunez-Yanez, M Hosseinabady, A Beldachi IEEE Transactions on Computers 65 (5), 1484-1493, 2015 | 47 | 2015 |
| Differential patterning of neuronal, glial and neural progenitor cells on phosphorus-doped and UV irradiated diamond-like carbon EM Regan, JB Uney, AD Dick, Y Zhang, J Nunez-Yanez, JP McGeehan, ... Biomaterials 31 (2), 207-215, 2010 | 47 | 2010 |
| A streaming dataflow engine for sparse matrix-vector multiplication using high-level synthesis M Hosseinabady, JL Nunez-Yanez IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 46 | 2019 |
| Run-time power gating in hybrid ARM-FPGA devices M Hosseinabady, JL Nunez-Yanez 2014 24th International Conference on Field Programmable Logic and …, 2014 | 42 | 2014 |
| Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication: Innovations for Computational Processing and Communication JS Shen, PA Hsiung IGI Global, 2010 | 42 | 2010 |
| Adaptive stochastic routing in fault-tolerant on-chip networks W Song, D Edwards, JL Nunez-Yanez, S Dasgupta 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 32-37, 2009 | 40 | 2009 |
| Adaptive voltage scaling with in-situ detectors in commercial FPGAs JL Nunez-Yanez IEEE Transactions on Computers 64 (1), 45-53, 2014 | 39 | 2014 |
| Adaptive voltage scaling in a dynamically reconfigurable FPGA-based platform A Nabina, JL Nunez-Yanez ACM Transactions on Reconfigurable Technology and Systems (TRETS) 5 (4), 1-22, 2012 | 38 | 2012 |
| Dynamic reconfiguration optimisation with streaming data decompression A Nabina, JL Nunez-Yanez 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 35 | 2010 |
| A Novel Control System Processor and Its VLSI Implementation X Wu, VA Chouliaras, JL Nunez-Yanez, RM Goodall IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (3), 217-228, 2008 | 35 | 2008 |
| Adaptive event-triggered anomaly detection in compressed vibration data Y Zhang, P Hutchinson, NAJ Lieven, J Nunez-Yanez Mechanical Systems and Signal Processing 122, 480-501, 2019 | 34 | 2019 |
| Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip J Nunez-Yanez, G Lore Microprocessors and Microsystems 37 (3), 319-332, 2013 | 32 | 2013 |
| Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems JL Nunez-Yanez, D Edwards, AM Coppola IET Computers & Digital Techniques 2 (3), 184-198, 2008 | 32 | 2008 |
| Simultaneous multiprocessing in a software-defined heterogeneous FPGA J Nunez-Yanez, S Amiri, M Hosseinabady, A Rodríguez, R Asenjo, ... The Journal of Supercomputing 75, 4078-4095, 2019 | 31* | 2019 |
| High-performance arithmetic coding VLSI macro for the H264 video compression standard JL Nunez, VA Chouliaras IEEE Transactions on Consumer Electronics 51 (1), 144-151, 2005 | 31 | 2005 |
| Accurate power control and monitoring in ZYNQ boards AF Beldachi, JL Nunez-Yanez 2014 24th International Conference on Field Programmable Logic and …, 2014 | 29 | 2014 |
vassilios chouliarasSenior Lecturer in Microelectronics and Computer Architecture, Loughborough University, UK確認したメール アドレス: lboro.ac.uk